WM8950GEFL/V Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8950GEFL/V Datasheet PDF : 52 Pages
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Preliminary Technical Data
CONTROL INTERFACE TIMING – 2-WIRE MODE
SDIN
SCLK
t3
t6
t1
t5
t2
t7
t9
t3
t4
WM8950
t8
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
Test Conditions
DCVDD=1.8V, DBVDD=AVDD=SPKVDD=3.3V, DGND=AGND=SPKGND=0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK =
256fs, 24-bit data, unless otherwise stated.
PARAMETER
Program Register Input Information
SCLK Frequency
SCLK Low Pulse-Width
SCLK High Pulse-Width
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
Pulse width of spikes that will be suppressed
SYMBOL
t1
t2
t3
t4
t5
t6
t7
t8
t9
tps
MIN
0
1.3
600
600
600
100
600
0
TYP
MAX
UNIT
526
kHz
us
ns
ns
ns
ns
300
ns
300
ns
ns
900
ns
5
ns
w
PTD Rev 2.1 June 2005
11
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