WM8608EFT/V Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM8608EFT/V

5 to 7.1 Channel PWM Controller

Wolfson Microelectronics plc 

WM8608

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Test Conditions

AVDD, BVDD, DVDD = 2.7 to 3.3V, AGND, DGND, BGND = 0V, TA = -20 to +85oC, fs = 44.1kHz/48kHz, MCLK = 256fs unless

stated.

PARAMETER

PWM buffer drive strength

SYMBOL

Isource

Isink

TEST CONDITIONS

CMOS

20pF load

MIN

254

254

TYP

MAX

UNIT

mA

mA

PWM pulse repetition rate

fPWM

fs = 44.1kHz

352.8

kHz

fs = 48kHz

384

kHz

Notes:

1. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’

weighted over a 20Hz to 20kHz bandwidth.

2. All performance measurements done with 20kHz AES17 low pass filter, except where noted an A-weight filter is used.

Failure to use such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in

the Electrical Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect

dynamic specification values.

3. Parameter guaranteed by design.

4. Validated using the following filter

PARAMETER

Filter

Stopband

SYMBOL TEST CONDITIONS

MIN

-3dB

TYP

1.00

MAX

UNIT

kHz

Note: A third order differential RC filter has been used

TERMINOLOGY

1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output

with no signal applied.

2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.

Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB

to it (e.g. THD+N @ -60dB= -32dB, DR= 92dB).

3. THD+N (dB) - THD+N is a ratio, of the RMS values, of (Noise + Distortion)/Signal.

POWER CONSUMPTION

MODE DESCRIPTION

TYPICAL SUPPLY CURRENTS

[mA]

TOTAL CURRENT TOTAL POWER

[mA]

[mW]

IAVDD

AVDD, DVDD, BVDD = 3.3V

OFF

0

Standby

0.02

Mute

1.76

Stereo

1.76

5.1

1.76

6.1

1.76

7.1

1.72

Table 1 Supply Current Consumption

IDVDD

IBVDD

CMOS LVDS

CMOS

0

0

0

0

0.28

0

0

0.30

27.2 7.55 29.0

36.5

27.7 7.55 29.0

37.0

28.1 7.55 29.0

37.5

29.6 7.55 29.0

38.9

29.9 7.55 29.0

39.2

LVDS

0

0.30

58.0

58.5

58.9

60.3

60.6

CMOS LVDS

0

0

0.99 0.99

121

191

122

193

124

194

128

199

129

200

Notes:

1. TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 27 kHz, 24-bit data

2. All figures are kHz 1kHz input sine wave @ 0dB.

w

PP Rev 1.5 March 2004

8

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