WM8608 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8608 Datasheet PDF : 54 Pages
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AUDIO INTERFACE TIMING – SLAVE MODE
tBCH
tBCL
BCLK
tBCY
LRCLK
tDS
DINFRONT
DINSRND
DINC_LFE
DINREAR
tLRH
tDH
tLRSU
WM8608
Figure 3 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,
unless otherwise stated.
PARAMETER
Audio Data Input Timing Information
BCLK cycle time
BCLK pulse width high
BCLK pulse width low
BCLK rise/fall times
LRCLK set-up time to BCLK rising edge
LRCLK hold time from BCLK rising edge
LRCLK rise/fall times
DINFRONT, DINSRND, DINC_LFE and DINREAR hold
time from BCLK rising edge
SYMBOL
tBCY
tBCH
tBCL
tLRSU
tLRH
tDH
MIN
TYP
MAX
UNIT
50
ns
20
ns
20
ns
5
ns
10
ns
10
ns
5
ns
10
ns
Table 5 Audio Interface Timing – Slave Mode
Note: BCLK period should always be greater than or equal to MCLK period.
w
PP Rev 1.5 March 2004
11
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