WM8602SEDS/RV Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM8602SEDS/RV

2.1 Channel PWM Controller

Wolfson Microelectronics plc 

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AUDIO INTERFACE TIMING – MASTER MODE

WM8602

BCLK

(Output)

LRCLK

(Output)

DIN

t

DL

t

DST

t

DHT

Figure 2 Digital Audio Data Timing – Master Mode (see Control Interface)

Test Conditions

AVDD, DVDD, BVDD = 3.3V, AGND, DGND, BGDN = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data,

unless otherwise stated.

PARAMETER

Audio Data Input Timing Information

LRCLK propagation delay from BCLK falling edge

DIN setup time to BCLK rising edge

DIN hold time from BCLK rising edge

SYMBOL

tDL

tDST

tDHT

MIN

10

10

TYP

MAX

UNIT

10

ns

ns

ns

Table 4 Audio Interface Timing – Master Mode

w

PP Rev 1.5 May 2004

9

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