WM8759 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8759 Datasheet PDF : 20 Pages
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WM8759
MASTER CLOCK TIMING
MCLK
tMCLKL
tMCLKH
tMCLKY
Figure 1 Master Clock Timing Requirements
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
System Clock Timing Information
MCLK Master clock pulse width high
MCLK Master clock pulse width low
MCLK Master clock cycle time
tMCLKH
tMCLKL
tMCLKY
MCLK Duty cycle
Time from MCLK stopping to power
down.
TEST CONDITIONS
MIN
8
8
20
40:60
1.5
DIGITAL AUDIO INTERFACE
tBCH
tBCL
BCKIN
tBCY
TYP
LRCIN
DIN
tDS
tLRH
tLRSU
tDH
Pre-Production
MAX
60:40
12
UNIT
ns
ns
ns
µs
Figure 2 Digital Audio Data Timing
Test Conditions
VDD = 5V, GND = 0V, TA = +25oC, fs = 48kHz, MCLK = 256fs unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
Audio Data Input Timing Information
BCKIN cycle time
tBCY
40
BCKIN pulse width high
tBCH
16
BCKIN pulse width low
tBCL
16
LRCIN set-up time to
tLRSU
8
BCKIN rising edge
LRCIN hold time from
tLRH
8
BCKIN rising edge
DIN set-up time to BCKIN
tDS
8
rising edge
DIN hold time from BCKIN
tDH
8
rising edge
w
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
PP Rev 3.1 June 2006
8
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