WM8759 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc
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WM8759 Datasheet PDF : 20 Pages
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Pre-Production
WM8759
1/fs
LRCIN
LEFT CHANNEL
RIGHT CHANNEL
BCKIN
DIN
1 BCKIN
123
MSB
n-2 n-1 n
LSB
1 BCKIN
123
MSB
n-2 n-1 n
LSB
Figure 3 I2S Mode Timing Diagram
RIGHT JUSTIFIED MODE
The WM8759 supports word lengths of 16-bits in right justified mode.
In right justified mode, the digital audio interface receives data on the DIN input. Audio Data is
time multiplexed with LRCIN indicating whether the left or right channel is present. LRCIN is also
used as a timing reference to indicate the beginning or end of the data words.
In right justified mode, the minimum number of BCKINs per LRCIN period is 2 times the selected
word length. LRCIN must be high for a minimum of word length BCKINs and low for a minimum of
word length BCKINs. Any mark to space ratio on LRCIN is acceptable provided the above
requirements are met.
In right justified mode, the LSB is sampled on the rising edge of BCKIN preceding a LRCIN
transition. LRCIN is high during the left samples and low during the right samples.
LRCIN
BCKIN
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DIN
123
14 15 16
123
14 15 16
MSB
LSB
MSB
LSB
Figure 4 Right Justified Mode Timing Diagram
DSP MODE
In DSP/PCM mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising
edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows
left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused
BCLK cycles between the LSB of the right channel data and the next sample.
In device master mode, the LRC output will resemble the frame pulse shown in Figure 5 and Figure 6. In
device slave mode, Figure 7 and Figure 8, it is possible to use any length of frame pulse less than 1/fs,
providing the falling edge of the frame pulse occurs greater than one BCLK period before the rising edge
of the next frame pulse.
w
PP Rev 3.1 June 2006
11
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