WM8738 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM8738

24 Bit Stereo ADC

Wolfson Microelectronics plc 

WM8738

Production Data

In a real application the designer is unlikely to have control of the relative power up sequence of

AVDD and DVDD. Using the POR circuit to monitor CAP ensures a reasonable delay between

applying power to the device and Device Ready.

Figure 3 and Figure 4 show typical power up scenarios in a real system. Both AVDD and DVDD must

be established and CAP must have reached the threshold Vporr before the device is ready and can be

written to. Any writes to the device before Device Ready will be ignored.

Figure 3 shows DVDD powering up before AVDD. Figure 4 shows AVDD powering up before DVDD.

In both cases, the time from applying power to Device Ready is dominated by the charge time of

CAP.

A 10uF cap is recommended for decoupling on CAP. The charge time for CAP will dominate the

time required for the device to become ready after power is applied. The time required for VMIDADC

to reach the threshold is a function of the CAP resistor string and the decoupling capacitor. The

Resistor string has a typical equivalent resistance of 50kΩ (+/-20%). Assuming a 10uF capacitor, the

time required for CAP to reach threshold of 1V is approx 110ms.

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PD Rev 4.4 August 2006

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