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WM2630 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM2630 Datasheet PDF : 13 Pages
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WM2630
SERIAL INTERFACE
Production Data
SCLK
DIN
X1
tSUD
X
D15
DOUT
FS
(µC MODE)
FS
(DSP MODE)
X
D15 *
tWHFS tSUFSCLK
tWLFS
tWL tWH
2
tHD
D14
3
D13
4
2
D14 *
D13 *
D12 *
* DIN data from previous word
(delayed by 16 clock cycles)
No high to low transitions
16
X
D1
D1 *
D0
X
D0 *
X
tSUC16-FS
Figure 1 Timing Diagram
SYMBOL
tSUFSCLK
tC16-FS
tWLOADB
tWH
tWL
tSUD
tHD
tWHFS
tWLFS
ts
TEST
CONDITIONS
Setup time, FS pin low before first falling edge of SCLK
Setup time, 16th falling clock edge after FS low to rising edge of FS (only
used in microcontroller mode)
Pulse duration, LOADB low
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
Pulse duration, FS low
DAC Output settling time
MIN
TYP MAX UNIT
8
ns
10
ns
10
ns
16
ns
16
ns
8
ns
5
ns
10
ns
10
ns
see Dynamic DAC Specifications
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
6

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