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WM2630 Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM2630 Datasheet PDF : 13 Pages
First Prev 11 12 13
Production Data
WM2630
DAC A TO H CODE REGISTERS
Addresses 0 to 7 are the DAC registers. The data written to these registers is transferred to the
respective DAC when the LOADB input (pin 18) is low. For instantaneous updating, LOADB can be held
low permanently.
CONTROL REGISTER 0
Control register 0 (address 8) is used to select functions that apply to the whole IC, such as Power Down
and Data Input Format.
BIT
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function
X
X X X X X X PD DO R1 R0 IM
Default
X
X XXXXX 0
0
0
0
0
Table 5 Register Map
BIT
DESCRIPTION
PD
Full device Power Down
DO
DOUT Enable
R1
Int / Ext Reference Select
R0
Internal Reference Select
IM
Input Mode
X
Reserved
Table 6 Register Map
0
Normal
Disabled
External
1.024V
Straight Binary
1
Power Down
Enabled
Internal
2.048V
Two’s Complement
CONTROL REGISTER 1
Control register 1 (address 9) is used to power down individual pairs of DACs and select their settling
time. Powering down a pair of DACs disables their amplifiers and reduces the power consumption of the
device. The settling time in fast mode is typically 1µs. In slow mode, the settling time is typically 3µs and
power consumption is reduced.
BIT
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Function
Default
X
X
X
X PGH PEF PCD PAB
SGH
SEF
SCD
SAB
X
X XX0 0 0 0
0
0
0
0
Table 7 Register Map
BIT
DESCRIPTION
PXY
Power Down DACs X and Y
SXY
Speed Setting for DACs X and Y
Table 8 Register Map
0
Normal
Slow
1
Power Down
Fast
DAC PRESET REGISTER
The Preset register (address 10) makes it possible to update all eight DACs at the same time. The value
stored in this register becomes the digital input to all the DACs when the asynchronous PREB input (pin
5) is driven low. If no data has previously been written to the preset register, all DACs are set to zero
scale.
TWO-CHANNEL REGISTERS
The two-channel registers (addresses 12 to 15) provide a ‘differential output’ function where writing data
to one DAC will automatically write the complement to the other DAC in the pair. For example, writing a
hexadecimal value of FFFF to address 12 will set DAC A to full scale and DAC B to zero scale.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.1 February 2001
11

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