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WM2627

Quad 8-Bit Serial Input Voltage Output DAC

Wolfson Microelectronics plc 

WM2627

Production Data

SERIAL INTERFACE

To start transferring data, the device first has to be enabled with NCS set to low. Then, a falling edge

of FS starts shifting the data bit-per-bit (starting with the MSB) to the internal register on the falling

edges of SCLK. After 16 bits have been transferred, the next rising edge on SCLK or FS causes the

content of the shift register to be moved to the DAC holding latch. If NLDAC is low, the DAC latch will

also be updated immediately.

The serial interface of the device can be used in two basic modes:

• four wire (with chip select)

• three wire (without chip select)

Using chip select (four wire mode), it is possible to have more than one device connected to the serial

port of the data source (DSP or microcontroller). If there is no need to have more than one device on

the serial bus, then NCS can be tied low.

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

fSCLKmax =

1

tWCH min+ tWCL min

=

20MHz

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC

settling time to 8 bits limits the update rate for large input step transitions.

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the

8-bit data word. D15-D12 hold the programmable options.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A1 A0 PWR SPD

New DAC value (8 bits)

0000

Table 2 Register Map

DAC ADDRESSING

A particular DAC (A, B, C, D) within the device is selected by A1 and A0 within the input word.

A1

A0

0

0

0

1

1

0

1

1

DAC ADDRESS

DAC A

DAC B

DAC C

DAC D

PROGRAMMABLE SETTLING TIME (SPD – BIT D12)

Settling time is a software selectable 2.5µs or 8.5µs, typical to within ±0.1LSB of final value. This is

controlled by the value of SPD – Bit D12 and an associated DAC address. A ONE defines a settling

time of 2.5µs, a ZERO defines a settling time of 8.5µs for that DAC.

PROGRAMMABLE POWER DOWN

The power down function is controlled by PWR - Bit D13 and an associated DAC address. A ZERO

configures that DAC as active, a ONE configures that DAC into power down mode.

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 April 2001

9

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