WM2623CD Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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Fabricante

WM2623CD

Low Power 8-bit Serial Input DAC

Wolfson Microelectronics plc 

Production Data

SERIAL INTERFACE

SCLK

DIN

1

tSUD

tHD

D15

tSUCSFS

tWL

tWH

2

3

D14

D13

NCS

tWHFS

FS

tSUFSCLK

4

5 15

16

D12

D1

D0

WM2623

tSUC16CS

tSUC16FS

Figure 1 Timing Diagram

Test Conditions:

RL = 10kΩ, CL = 100pF. VDD = 5V ±10%, VREF = 2.048V and VDD = 3V ±10%, VREF = 1.024V over recommended operating

free-air temperature range (unless noted otherwise).

SYMBOL TEST CONDITIONS

MIN

tSUCSFS

Setup time NCS low before falling FS edge.

10

tSUFS

Setup time FS low before first falling SCLK edge.

8

Setup time, 16th falling SCLK edge after FS low on

tSUC16FS

which data bit D0 is sampled before rising edge of FS.

10

Setup time, 16th rising SCLK edge (first after data bit

D0 sampled) before NCS rising edge. If FS is used

tSUC16CS

instead of the 16th rising edge to update the DAC, this

10

setup time is between the FS rising edge and the NCS

rising edge.

tWH

Pulse duration, SCLK high.

25

tWL

Pulse duration, SCLK low.

25

tSUD

Setup time, data ready before SCLK falling edge.

8

tHD

Hold time, data held valid after SCLK falling edge.

5

tWHFS

Pulse duration, FS high.

20

TYP

MAX

UNIT

ns

ns

ns

ns

ns

ns

ns

ns

ns

WOLFSON MICROELECTRONICS LTD

PD Rev 1.0 October 2000

5

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