WM2617ID Ver la hoja de datos (PDF) - Wolfson Microelectronics plc

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WM2617ID

Dual 10-Bit Serial DAC with Power Down

Wolfson Microelectronics plc 

WM2617

DEVICE DESCRIPTION

Production Data

GENERAL FUNCTION

The device uses a resistor string network buffered with an op amp to convert 10-bit digital data to

analogue voltage levels (see Block Diagram). The output voltage is determined by the reference

input voltage and the input code according to the following relationship:

Output voltage = ( ) 2 VREF code

1024

INPUT

11

1111

1111

:

10

0000

0001

10

0000

0000

01

1111

1111

:

00

0000

0001

00

0000

0000

OUTPUT

( ) 2 VREF 1023

1024

:

( ) 513

2 VREF

1024

( ) 2 VREF 512 = VREF

1024

( ) 2 VREF 511

1024

:

( ) 2 VREF 1

1024

0V

Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2

POWER ON RESET

An internal power-on-reset circuit resets the DAC registers to all 0s on power-up.

BUFFER AMPLIFIER

The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a

2kΩ load with a 100pF load capacitance.

EXTERNAL REFERENCE

The reference voltage input is buffered which makes the DAC input resistance independent of

code. The REFIN input resistance is 10MΩ and the REFIN input capacitance is typically 5pF. The

reference voltage determines the DAC full-scale output.

SERIAL INTERFACE

When chip select (NCS) is low, the input data is read into a 16-bit shift register with the input data

clocked in most significant bit first. The falling edge of the SCLK input shifts the data into the

input register. After 16 bits have been transferred, the next rising edge on SCLK or NCS then

transfers the data to the DAC latch. When NCS is high, input data cannot be clocked into the

input register (see Table 2).

SERIAL CLOCK AND UPDATE RATE

Figure 1 shows the device timing. The maximum serial rate is:

fSCLKmax =

1

tWCH min+ tWCL min

=

20MHz

The digital update rate is limited to an 800ns period, or 1.25MHz frequency. However, the DAC

settling time to 10 bits limits the update rate for large input step transitions.

SOFTWARE CONFIGURATION OPTIONS

The 16 bits of data can be transferred with the sequence shown in Table 2. D11-D2 contains the

10-bit data word. D15-D12 hold the programmable options which are summarized in Table 3.

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

Program Bits

New DAC value (10 bits)

xx

Table 2 Register Map

WOLFSON MICROELECTRONICS LTD

PD Rev 1.1 October 2000

6

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