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W83194BR-603

Winbond Clock Generator For INTEL P4 Springdale Series Chipset

Winbond 

W83194BR-603/W83194BG-603

CLOCK GEN. FOR INTEL P4 SPRINGDALE/PRESCOTT SERIES CHIPSET

7. I2C CONTROL AND STATUS REGISTERS

7.1 Register 0: Frequency Select Register (Default = 10h)

BIT

NAME

7 SSEL [4]

PWD

DESCRIPTION

0 Frequency selection by software via I2C

6 SSEL [3]

0

5 SSEL [2]

0

4 SSEL [1]

1

3 SSEL [0]

0

2 EN_SSEL

0 Enable software program FS [4:0].

0 = Select frequency by hardware.

1= Select frequency by software I2C - Bit 7~ 3.

1 EN_SPSP

0 Enable Spread Spectrum in the frequency table.

0 = Normal

1 = Spread Spectrum enabled

0 EN_SAFE_FREQ 0 Enable reload safe frequency when the watchdog is timeout.

0 = reload the FS [4:0] latched pins when watchdog time out.

1 = reload the safe frequency bit defined at Register 5 bit 4~0.

7.2 Register 1: CPU Clock Register (1 = Enable, 0 = Stopped) (Default: E2h)

BIT

PIN NO PWD

DESCRIPTION

7

45,44

1 CPUT/C_ITP output control.

6

42,41

1 CPUT1 / C1 output control.

5

39,38

1 CPUT0 / C0 output control.

4

-

X Power on latched value of FS4 pin. Default: 0, (Read Only).

3

-

X Power on latched value of FS3 pin. Default: 0. (Read Only).

2

-

X Power on latched value of FS2 pin. Default: 0. (Read Only).

1

-

X Power on latched value of FS1 pin. Default: 1. (Read Only).

0

-

X Power on latched value of FS0 pin. Default: 0. (Read Only).

Publication Release Date: March, 2006

-7-

Revision 0.7

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