W78E365A40PL Ver la hoja de datos (PDF) - Winbond

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W78E365A40PL

8-bit CMOS microcontroller

Winbond 

W78E365/W78E365A

6.6.1 Port Options Register

Bit:

7

6

5

4

-

-

-

-

Mnemonic: POR

3

2

-

-

Address: 86H

1

0

-

P0UP

P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or

standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When

the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with

internal pull-up that is structurally the same Port2.

6.6.2 INT2 / INT3

Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external

interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are

determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is

bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To

set/clear bits in the XICON register, one can use the "SETB ( CLR ) bit" instruction. For example,

"SETB 0C2H" sets the EX2 bit of XICON.

XICON - external interrupt control (C0H)

PX3

EX3

IE3

IT3

PX2

EX2

IE2

IT2

PX3: External interrupt 3 priority high if set

EX3: External interrupt 3 enable if set

IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced

IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software

PX2: External interrupt 2 priority high if set

EX2: External interrupt 2 enable if set

IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced

IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software

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Publication Release Date: January 10, 2007

Revision A9

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