W181(2000) Ver la hoja de datos (PDF) - Cypress Semiconductor

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componentes Descripción

Fabricante

W181
(Rev.:2000)

Peak Reducing EMI Solution

Cypress Semiconductor 

W181

Application Information

Recommended Circuit Configuration

For optimum performance in system applications the power

supply decoupling scheme shown in Figure 4 should be used.

VDD decoupling is important to both reduce phase jitter and

EMI radiation. The 0.1-µF decoupling capacitor should be

placed as close to the VDD pin as possible, otherwise the in-

creased trace inductance will negate its decoupling capability.

The 10-µF decoupling capacitor shown should be a tantalum

type. For further EMI protection, the VDD connection can be

made via a ferrite bead, as shown.

Recommended Board Layout

Figure 5 shows a recommended 2-layer board layout.

Reference Input

1

NC 2

GND 3

4

8

7

6

5

R1

Clock

Output

C1

0.1 µF

3.3 or 5V System Supply

FB

C2

10 µF Tantalum

Figure 4. Recommended Circuit Configuration

Reference Input

NC

G

C1 =

C2 =

R1 =

High frequency supply decoupling

capacitor (0.1-µF recommended).

Common supply low frequency

decoupling capacitor (10-µF tantalum

recommended).

Match value to line impedance

FB = Ferrite Bead

G = Via To GND Plane

C1

G

Power Supply Input

(3.3 or 5V)

R1

G

C2

FB

Figure 5. Recommended Board Layout (2-Layer Board)

Ordering Information

Ordering Code

Freq. Mask

Code

W181

01, 02, 03

51, 52, 53

W181

01

Document #: 38-00790-B

Package

Name

G

Package Type

8-pin Plastic SOIC (150-mil)

X

14-pin Plastic TSSOP

Clock Output

7

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