VV6404 Ver la hoja de datos (PDF) - STMicroelectronics
Número de pieza
componentes Descripción
Fabricante
VV6404 Datasheet PDF : 54 Pages
| |||
VV5404 & VV6404
4.6.1 Power-Up/Down (Figure 12)
On power-up all of the databus lines will go high Immediately (FH), to indicate that the device is “present” and the
device enters it low-power mode (Section 4.6.2).
When the Video Processor is reset the following sequence should be executed to ensure that the VM6404 starts to
generate video data:
1. After the Video Processor has been released from reset, the sensor clock, CLKI, should be enabled immedi-
ately
2. After waiting for at least 16 CLKI clock cycles, a “Soft Reset” command should be issued to the sensor. This is
necessary to ensure that the sensor is brought into a known state. If the sensor is not present then the serial
interface communications by Video Processor will not be acknowledged.
3. Poll for 32 consecutive FH values on the data bus, if this condition is satisfied then the sensor is present. The
Video processor should set the camera_present flag.
4. Determine if the serial CMOS E2PROM containing the defectivity map for the sensor is present and down-load
the values.
5. Disable the sensor clock CKI.
6. The Video Processor should generate the VP_Ready interrupt.
7. Once the host software serviced the VP_Ready interrupt, then the sensor and video processor is ready to gen-
erate video data.
8. To enable video data, the host software, sets the low-power mode bit low. The video processor must enable
CLKI at least 16 CLKI clock cycles before issuing the “Exit Low-Power Mode” command via the serial interface.
After the “Exit Low-Power Mode” command has been sent the sensor will output for one frame, a continuous stream
of alternating 9H and 6H values on D[3:0]. By locking onto the resulting 0101/1010 patterns appearing on the data bus
lines the video processor can determine the best sampling position for the nibble data. After the last 9H 6H pair has
been output the databus returns to FH until the start of fifth frame after CKI has been enabled when the first active
frame output. After the video processor has determined the correct sampling position for the data, it should then wait
for the next start of frame line (SOF).
If the video processor detects 32 consecutive 0H values on the data bus, then the sensor has been removed. The
sensor clock, CKI, should be held low.
4.6.2 Low-Power Mode (Figure 10)
Under the control of the serial interface the sensor analogue circuitry can be powered down and then be powered up.
When the low-power bit is set via the serial interface, all the databus lines will go high at the end of the end of frame
line of the current frame. At this point the analogue circuits in the sensor will power down. The system clock must
remain active for the duration of low power mode.
Only the analogue circuits are powered down, the values of the serial interface registers e.g. exposure and gain are
preserved.
The internal frame timing is reset to the start of a video frame on exiting low-power mode.
In a similar manner to the previous section, the first frame after the serial comms contains a continuous stream of
alternating 9H and 6H to allow the video processor to re-confirm its sampling position. Then three frames latter the
first start of frame line is generated.
4.6.3 Sleep Mode (Figure 11)
Sleep mode is similar to the low-power mode, except that analogue circuitry remains powered. When the sleep
command is received via the serial interface the pixel array will be put into reset and the data lines all will go high at
the end of the current frame. Again the system clock must remain active for the duration of sleep mode.
When sleep mode is disabled, the CMOS sensor’s frame timing is reset to the start of a frame. During the first frame
after exiting from sleep mode the databus will remain high, while the exposure value propagates through the pixel
array. At the start of the second frame the first start of field line will be generated.
CD5404-6404F-A
18/54
Share Link: 