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VSC837UG

3.2Gb/s 68x68 Crosspoint Switch

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Data Sheet

VSC837

3.2Gb/s

68x68 Crosspoint Switch

Programming Interface

Parallel Mode

In parallel mode (SERIAL=0, BURST=0), the binary word on INCHAN[6:0] is the numerical identifier of

the input that will be routed to the specified output. OUTCHAN[6:0] is the numerical identifier of the output

being programmed. A rising edge on the LOAD signal will transfer the programming data to the shadow regis-

ter in the program memory. Raising CONFIG (asynchronously) will transfer the programming data to the main

latches in the program memory and cause the internal select signals in the core to re-configure the multiplexer.

Lowering CONFIG will latch the main latches. CONFIG may be tied HIGH to enable programming take effect

instantaneously.

This interface may be used with multiplexed address/data buses by using only INCHAN[6:0] without

OUTCHAN[6:0] and dropping ALE when the address of the output to be programmed is present on

INCHAN[6:0]. After the address is latched, the input address may be presented on INCHAN[6:0] and pro-

gramming proceeds as above.

No read-back capability is provided in parallel mode. Read-back for diagnostic purposes is provided in

serial mode via the scan function.

Serial Mode

In serial mode (SERIAL=1, BURST=0), the INCHAN0 pin becomes the serial data input and the

INCHAN1 pin becomes the serial clock (rising edge triggered). A serial word of the form [Output][Input] is

shifted into the internal shift register, and the LOAD pin is asserted (HIGH) coincident with the last bit of the

data word to signal that the word is to be applied. This transfers the input identifier to the shadow register of the

addressed output. CONFIG is then applied (asynchronously) to transfer one or more program commands to the

main latches of the program memories.

The SDOUT pin follows the data on the INCHAN0_SDIN pin 14 clock cycles later. This enables the user

to chain the serial ports of several crosspoints, shift program data for all switches through such a chain, and

assert LOAD on all switches simultaneously to program all of the connections simultaneously.

The output field is 7 bits long, representing the binary numerical identifier of the output to be programmed.

The input field is 7 bits long, representing the numerical identifier of the input that will be routed to the speci-

fied output.

Serial Read-Back

Read-back of the program memory contents is accomplished in serial mode by setting the ALE_SCN pin

HIGH. This will serially shift out the contents of the main latches in the program memories, slice 68 first and

slice 0 last, and MSB-first, LSB-last for each 7-bit word. One rising edge of INCHAN1_SCLK with

ALE_SCN=0 and SERIAL=1 must occur to load the entire 483-bit shift register prior to shifting out data. At a

clock rate of 66MHz, this operation takes 7.26µs.

G52309-0, Rev 3.0

02/16/01

© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012

Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com

Internet: www.vitesse.com

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