VITESSE
SEMICONDUCTOR CORPORATION
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Preliminary Datasheet
VSC8164
Figure 1: Split-end DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VCC
VSC8164
Zo
R1
R1 downstream
Zo
R1||R2 = Zo , R1 = 125Ω R2 = 83Ω
R2
R2
VCCR2 + VEER1
R1+R2
= VTerm
VEE
Figure 2: Traditional DC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8164
Zo
downstream
R1 =50Ω
VCC-2V
R1 =50Ω
VCC-2V
Figure 3: AC Termination of Low Speed LVPECL CLK16O, CLK32O, D[15:0] Outputs
VSC8164
Zo
Zo
50Ω
100nF
50Ω 100nF
VCC-2V
downstream
bias point
generated
internally
Page 2
VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
G52239-0, Rev. 3.3
5/17/00