VSC7133 Ver la hoja de datos (PDF) - Vitesse Semiconductor
Número de pieza
componentes Descripción
Fabricante
VSC7133 Datasheet PDF : 18 Pages
| |||
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7133
10-bit Transceiver for Fibre
Channel and Gigabit Ethernet
RCLK
RCLKN
R(0:9)
Figure 5: Receive Timing Waveforms
T4
Data Valid
T1
T2
Data Valid
T3
Data Valid
Table 3: Receive AC Characteristics
Parameters
Description
Min.
Max. Units
Conditions
T1
TTL Outputs Valid prior
to RCLK/RCLKN rise
4.0
3.0
—
—
@ 1.0625Gb/s
ns @ 1.25Gb/s
T2
TTL Outputs Valid after
RCLK or RCLKN rise
3.0
2.0
—
—
@ 1.0625Gb/s
ns @ 1.25Gb/s
T3
Delay between rising
edge of RCLK to rising
edge of RCLKN
10 x TRX
-500
10 x TRX
+500
ps
TRX is the bit period of the
incoming data on Rx.
T4
Period of RCLK and
RCLKN
1.98 x
TREFCLK
2.02 x
TREFCLK
Whether or not locked to
ps serial data.
R(0:9), COMDET,
TR, TF
SIGDET, RCLK and
—
RCLKN rise and fall time
2.4
ns
Between VIL(MAX) and
VIH(MIN), into 10 pf. load.
RLAT
Latency from RX to
R(0:9)
12 bc + 1 ns 13 bc + 9 ns
bc
ns
bc = Bit clock
ns = Nano second
TLOCK*
Data acquisition lock time
—
1400
bc
8B/10B IDLE pattern.
bc= bit clocks
* Note: Probability of recovery for data acquisition is 95% per Section 5.3 of FC-PH rev. 4.3
G52187-0 Rev. 2.4
1/17/00
© VITESSE SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896
Page 7
Share Link: 