VP211 Ver la hoja de datos (PDF) - Zarlink Semiconductor Inc
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VP211 Datasheet PDF : 8 Pages
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VP211
Layout And Grounding
As with all high speed A to D converters, careful
consideration must be given to the PCB layout. High
performance can be obtained from the VP211 by tying all
grounds to a solid low impedance ground plane. Separate
analog and digital ground planes with a single common link
under the device can also be used to help reduce the
amount of digital noise fed back into the analog section of the
converter.
The VP211 should be decoupled with low impedance
100nF ceramic capacitors close to the package pins to avoid
lead inductance effects and the decoupling on supply lines
should further be improved by using a 47µF tantalum
capacitor in parallel with a 100nF ceramic capacitor. If VCCA
is derived from VCCD, a small inductor should be used to
reduce digital noise on the analog power supply. Jitter and
noise on clock input pins must be minimised. Long clock
lines should therefore be avoided and all clock lines correctly
terminated. Cross talk of digital signals to the analog inputs
must also be prevented as sampling cross talk produces DC
offsets on the sampled data, for this reason analog inputs
should not be run next to clock or data lines. Device
connections to the ground plane should be as short as
possible.
CLKIN
50R
1.2µH
VINA
VCCA
47µ
VINB
Cc
50R
100n
Cc
50R
1
28
2
27
100n
3
26
4
25
100n
Ccomp
5 VP211 24
6
23
7
22
8
21
100n
9
20
100n
10
19
Ccomp
11
18
12
17
100n
13
16
14
15
A Channel
Data
100n
47µ
B Channel
Data
VCCD
100n
Analog Ground
Digital Ground
Fig.5 Applications diagram
Application Circuit
Fig.5 shows a typical applications circuit for the VP211.
The supply connections are made using separate low noise
digital and analog power supplies and VCCD is further
isolated from VCCO using a 1.2µH inductor.
The COMPA and COMPB pins must be decoupled to
reduce any ripple at low frequencies which may distort the
ADC driver amplifier output, (see Fig.2.) The decoupling
capacitor value is determined by the required low frequency
performance of the system and can be obtained from the
following equation.
CComp = 75x10- 6
Fin x VRipple
A ripple voltage ≤ 10mV is recommended for good
system performance, e.g. If the analog input frequency Fin=
10KHz a value of 0.75µF is required for CComp.
To ensure effective A.C. coupling at low input
frequencies, the coupling capacitors on pins 6 and 11 can be
calculated from the high pass filter corner frequency
equation,
Fc =
1
2 x π x RC
where
Fc = Lower -3dB corner frequency
(R = Input Resistance, 25K typ. - 20K min)
6
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