VP2614 Ver la hoja de datos (PDF) - Mitel Networks
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VP2614 Datasheet PDF : 12 Pages
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VP2614
SUPPLEMENTARY NOTE:
To avoid problems with register loading, the VP2614 requires
two write operations with no read strobe in between. The
absence of chip enable with the read strobe does not prevent
this problem. Thus if I/Os are memory mapped it will be
necessary to externally gate the read strobe with chip enable
for the VP2614 and to do two writes for every load operation.
STATUS REGISTER A ( ADDRESS 0 )
BIT
FUNCTION
0
GSPARE Byte Available ( FIFO not Empty )
1
Freeze Frame
2
Buffer Full
3
Buffer Empty
4
Picture Information Ready
5-7
Unassigned
STATUS REGISTER B ( ADDRESS 1 )
BIT
FUNCTION
0
Frame Lock Lost
1
Frame Lock Achieved
2
Video Lock Lost
3
Video Lock Achieved
4 -7
Unassigned
CONTROL REGISTER A ( ADDRESS 2 )
BIT
FUNCTION ( when the bit is set )
0
Freeze Frame released by bit stream
1
Force Freeze Frame
2
Error interrupt only from Frame Lock
3
Enable EVT Interrupt
4
Enable ERR Interrupt
5
Video Hold
6
Clear Buffer
7
System Re-start
CONTROL REGISTER B ( ADDRESS 3 )
BIT
FUNCTION ( when the bit is set )
0
Re-lock to Picture Start Code
1-2
Unassigned
4
000 FEC Framing Off
5:3 101 FEC Framing On
6
Clear Video Lock Lost Counter
7
Clear other Counters apart from above
Note: Control Register B must be loaded with the required
values before Register A is programmed.
USER READABLE COUNTERS
ADDRESS FUNCTION
4
FEC Frame Count
5
Filled Frames Count
9
Video Lock Lost Count
6
PICTURE STATUS REGISTERS
10
Temporal Reference Register
11
Picture Information ( see below )
12
First PSPARE Byte
13
Second PSPARE Byte
14
Top of GSPARE Stack
PICTURE INFORMATION REGISTER ( ADDRESS 11)
BIT
FUNCTION
7
PSPARE Byte 2 Valid (cleared by reading byte)
6
PSPARE Byte 1 Valid (cleared by reading byte)
5
Split screen
4
Document camera
3
Freeze frame
2
CIF/QCIF
1:0
Set to one
[Bit 0 is LSB]
A master - slave arrangement is used for the Picture
Status Registers, and the slave is not updated for the duration
of the host read operation plus 32 system clock cycles.
Reading any of the counter values ( address 4-9 ) or any
Picture Status Register ( address 10-13 ) causes all values in
the respective blocks to be frozen for 32 clocks, thus allowing
a complete snapshot to be taken of the respective values.
Two bytes of PSPARE data are stored and further bytes
will be lost. Note that the VP2612 Video Multiplexer presently
only provides one byte of PSPARE information. A FIFO is
provided to provide storage for 12 GSPARE bytes, and a
status bit is provided to indicate that this FIFO is not empty,
and that the byte at the top of the stack should be read.
RESET OPERATION
In addition to the hardware reset there are several soft-
ware reset options which are selective in their action. The
hardware reset input will initialize all the internal circuit blocks,
and will clear all status registers, error counters, and address
pointers. The bits in Control Registers A and B are cleared
except that the Video Hold Bit in Register A is set, and Bits 0,4,
and 5 are set in Register B. The device will thus re-lock to a
Picture Start Code, will correct 2 bit errors, and FEC Framing
will be on. The circuit which interfaces to the VP2615 Decoder
is reset to the end of picture condition ( Macroblock 33 in GOB
12 ).
The System Re-start bit ( Bit 7 in Control Register A ) will
clear all status bits and will initialize the bitstream decoder, the
forward error corrector, and the buffer alignment modules. It
should be used if there has been an interruption in the
bitstream, and does not affect the circuit producing GOB's and
macroblocks for the VP2615 Decoder. Thus, after the re-start,
Video Lock can be obtained on a GOB boundary, and Fixed
macroblocks can be generated for missing macroblocks within
the same picture.
The Clear Buffer bit ( Bit 6 in Control Register A ) will reset
the read and write address pointers for the external buffer. A
full software restart requires both Bit 7 and Bit 6 to be set.
Two bits are also provided in Control Register B for reset
operations. One will clear the Video Lock Lost counter, the
other clears the FEC frame counter, the Filled Frames coun-
ter, and the three error counters in the error detection circuit.
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