VN5050JTR-E Ver la hoja de datos (PDF) - STMicroelectronics
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VN5050JTR-E Datasheet PDF : 31 Pages
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Block diagram and pin description
Figure 2. Configuration diagram (top view)
N.C.
1
12
GND
2
11
INPUT
3
10
STATUS_DIS
4
9
STATUS
5
8
N.C.
6
7
TAB = Vcc
N.C.
OUTPUT
OUTPUT
OUTPUT
OUTPUT
N.C.
VN5050J-E
Note:
PowerSSO-12
The above pin configuration reflects the changes notified with PCN-APG-BOD/07/2886. The
new pinout is backaward compatible with existing PCB layouts where pins #1 and #6 are
connected to Vcc and/or pins #7 and 12 are connected to OUTPUT. For new PCB designs,
these pins should be left unconnected.
Table 3. Suggested connections for unused and N.C. pins
Connection / Pin
STATUS
N.C. OUTPUT
INPUT
STAT_DIS
Floating
To ground
(1) Not recommended.
X
N.R.(1)
X
X
X
X
X
N.R.
Through 10K Through 10K
resistor
resistor
6/31
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