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VN5050JTR-E Ver la hoja de datos (PDF) - STMicroelectronics

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VN5050JTR-E Datasheet PDF : 31 Pages
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Electrical specifications
VN5050J-E
Figure 4. Status timings
OPEN LOAD STATUS TIMING (without external pull-up) OPEN LOAD STATUS TIMING (with external pull-up)
VIN
IOUT < IOL
VIN
IOUT < IOL
VOUT < VOL
VOUT > VOL
VSTAT
tDOL(on)
tPOL
VSTAT
tDOL(on)
OUTPUT STUCK TO VCC
VIN
IOUT > IOL
VOUT > VOL
VSTAT
tDOL(on)
tDSTKON
OVER TEMP STATUS TIMING
Tj > TTSD
VIN
VSTAT
tSDL
tSDL
Truth Table
Table 12. Truth table
Conditions
INPUT
OUTPUT
STATUS (VSD=0V)(1)
L
L
H
Normal operation
H
H
H
L
L
H
Current limitation
H
X
H
L
L
H
Overtemperature
H
L
L
L
L
X
Undervoltage
H
L
X
L
H
Lv
Output voltage > VOL
H
H
H
L
L
H(2)
Output current < IOL
H
H
L
(1) If the VSD is high, the STATUS pin is in a high impedance.
(2) The STATUS pin becomes high with a delay equal to tPOL after INPUT falling edge.
12/31

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