VIPER53 Ver la hoja de datos (PDF) - STMicroelectronics

Número de pieza

componentes Descripción

Fabricante

VIPER53

OFF LINE PRIMARY SWITCH

STMicroelectronics 

VIPer53DIP / VIPer53SP

charging current is reduced down to IDDch2 which

is about 0.6 mA. This lower current leads to a slope

change on the VDD rise. The device starts

switching for a VDD equal to VDDon, and the

auxiliary winding delivers some energy to the VDD

capacitor after the start-up time tss.

The charging current change at VDDoff allows a fast

complete start-up time tsu, and maintains a low

restart duty cycle. This is especially useful for short

circuits and overloads conditions, as described in

the following section.

SHORT-CIRCUIT AND OVERLOAD

PROTECTION

A VCOMPovl threshold of about 4.35 V has been

implemented on the COMP pin. When VCOMP goes

above this level, the capacitor connected on the

TOVL pin begins to charge. When reaching

typically 4 V (VOVLth), the internal mosfet driver is

disabled and the device stops switching. This state

is latched thanks to the regulation loop which

maintains the COMP pin voltage above the

VCOMPovl threshold. Since the VDD pin doesn’t

receive any more energy from the auxiliary

winding, its voltage drops down until it reaches

VDDoff and the device is reset, recharging the

VDD capacitor for a new restart cycle. Note that if

VCOMP drops down below the VCOMPovl threshold

for any reason during the VDD drop, the device

resumes switching immediately.

The device enters an endless restart sequence if

the overload or short circuit condition is

maintained. The restart duty cycle DRST is defined

as the time ratio for which the device tries to

restart, thus delivering its full power capability to

the output. In order to keep the whole converter in

a safe state during this event, DRST must be kept

as low as possible, without compromising the real

start up of the converter. A typical value of about

10 % is generally sufficient. For this purpose, both

VDD and TOVL capacitors can be used to satisfy

the following conditions:

COVL > 12.5 ⋅ 10–6 ⋅ ts s

CVDD

>

8

⋅

104

⋅





-----1-------

DRST

–

1

⋅

C-----O---V---L----⋅----I--D---D----c--h---2

VDDhyst

Refer to the previous start-up section for the

definition of tss, and CVDD must also be checked

against the limit given in this section. The

maximum value of the two calculus will be

adopted.

All this behavior can be observed on figure 4. In

Figure 8 the value of the drain current Id for

VCOMP=VCOMPovl is shown. The corresponding

parameter IDmax is the drain current to take into

account for design purpose. Since IDmax

represents the maximum value for which the

overload protection is not triggered, it defines the

power capability of the power supply.

TRANSCONDUCTANCE ERROR AMPLIFIER

The VIPer53 includes a transconductance error

amplifier. Transconductance Gm is the change in

output current ICOMP versus change in input

voltage VDD. Thus:

Gm

=

∂ICOMP

∂VDD

The output impedance ZCOMP at the output of this

amplifier (COMP pin) can be defined as:

ZCOMP

=

∂VCOMP

∂ICOMP

=

----1----

Gm

⋅

∂VC O M P

∂VDD

This last equation shows that the open loop gain

AVOL can be related to Gm and ZCOMP:

AVOL = Gm ⋅ ZCOMP

where Gm value for VIPer53 is typically 1.4 mA/V.

Gm is well defined by specification, but ZCOMP and

therefore AVOL are subject to large tolerances. An

impedance Z must be connected between the

COMP pin and ground in order to define accurately

the transfer function F of the error amplifier,

according to the following equation, very similar to

the one above:

F(s) = Gm ⋅ Z(s)

The error amplifier frequency response is shown in

figure 10 for different values of a simple resistance

connected on the COMP pin. The unloaded

transconductance error amplifier shows an internal

ZCOMP of about 140 KΩ. More complex

impedances can be connected on the COMP pin to

achieve different compensation methods. A

capacitor provides an integrator function, thus

eliminating the DC static error, and a resistance in

series leads to a flat gain at higher frequency,

Figure 18: Typical Compensation Network

VDD

OSC

15V

TOVL

DRAIN

COMP SOURCE

10nF

Rcomp

Ccomp

16/24

Share Link: