VDP313XY Ver la hoja de datos (PDF) - Micronas

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Fabricante

VDP313XY

Video Processor Family

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ADVANCE INFORMATION

VDP 313xY

2. Functional Description

2.1. Introduction

The VDP 313xY includes complete video, display and

deflection processing. All processing is done digitally,

the video frontend and video backend are interfacing

to the analog world. Most functions of the VDP can be

controlled by software via I2C-Bus interface (see

Section 2.14.1. on page 29).

2.2. Video Front End

rent sources. The clamping level is the back porch of

the video signal.

S-VHS chrominance is also AC coupled. The input pin

is internally biased to the center of the ADC input

range.

The chrominance inputs for YCRCB need to be AC

coupled using clamping capacitors. It is strongly rec-

ommended to use 5 MHz anti-alias low-pass filters on

each input. Each channel is sampled at 10.125 MHz

with a resolution of 8 bit and a clamping level of 128.

This block provides the analog interfaces to all video

inputs and mainly carries out analog-to-digital conver-

sion for the following digital video processing. A block

diagram is given in Fig. 2–1.

Most of the functional blocks in the front-end are digi-

tally controlled (clamping, AGC, and clock-DCO). The

control loops are closed by the Fast Processor (FP)

embedded in the video decoder.

2.2.1. Input Selection

Up to seven analog inputs can be connected. Four

inputs are for input of composite video or S-VHS lumi-

nance signal. These inputs are clamped to the sync

back porch and are amplified by a variable gain ampli-

fier. Two inputs are for connection of S-VHS car-

rier-chrominance signal. These inputs are internally

biased and have a fixed gain amplifier. For analog

YCRCB signals (e.g. from DVD players) the selected

luminance input is used together with CBIN and CRIN.

2.2.3. Automatic Gain Control

A digitally working automatic gain control adjusts the

magnitude of the selected baseband by +6/–4.5 dB in

64 logarithmic steps to the optimal range of the ADC.

The gain of the video input stage including the ADC is

213 steps/V with the AGC set to 0 dB.

The gain of the chrominance path in the YCRCB mode

is fix and adapted to a nominal amplitude of 0.7 Vpp.

However, if an overflow of the ADC occurs an

extended signal range of 1 Vpp can be selected.

2.2.4. Analog-to-Digital Converters

Two ADCs are provided to digitize the input signals.

Each converter runs with 20.25 MHz and has 8 bit res-

olution. An integrated bandgap circuit generates the

required reference voltages for the converters. The two

ADCs are of a 2-stage subranging type.

2.2.2. Clamping

The composite video input signals are AC coupled to

the IC. The clamping voltage is stored on the coupling

capacitors and is generated by digitally controlled cur-

2.2.5. Digitally Controlled Clock Oscillator

The clock generation is also a part of the analog front

end. The crystal oscillator is controlled digitally by the

control processor. The clock frequency can be

adjusted within ±150 ppm.

CVBS/Y VIN1

CVBS/Y VIN2

CVBS/Y VIN3

CVBS/Y VIN4

Chroma CIN1

Chroma

CIN2

CRIN

Chroma CBIN

Fig. 2–1: Video front-end

clamp

bias

clamp

AGC

+6/–4.5 dB

ADC

digital CVBS or Luma

gain

ADC

digital Chroma

reference

generation

DVCO

±150

ppm

system clocks

frequency

20.25 MHz

Micronas

7

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