V29C51400B Ver la hoja de datos (PDF) - Mosel Vitelic Corporation
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V29C51400B
Mosel Vitelic Corporation
V29C51400B Datasheet PDF : 16 Pages
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MOSEL VITELIC
V29C51400Tx8
16KB Boot Block
7FFFFH
7C000H
V29C51400Bx8
V29C51400T/V29C51400B
V29C51400Tx16
16KB Boot Block
3FFFFH
3E000H
V29C51400Bx16
00000H
3FFFH
00000H 16KB Boot Block 00000H
16KB Boot Block = 32 Sectors
BYTE MODE
00000H
00000H
1FFFH
16KB Boot Block 00000H
51400-11
16KB Boot Block = 32 Sectors
WORD MODE
World/Byte Configuration
The BYTE pin controls whether the device data
I/O pins I/O0-I/O15 operate in the byte or word
configuration. If the BYTE pin is set at logic ’1’, the
device is in word configuration, I/O0-I/O15 are
active and controlled by CE and OE.
If BYTE pin is set at logic ’0’, the device is in byte
configuration, and only data I/O pins I/O0-I/O7 are
active and controlled by CE and OE. The data I/O
pins I/O8-I/O14 are tri-stated, and the I/O15 pin is
used as an input for the LSB (A-1) address
function.
Functional Description
The V29C51400T/V29C51400B consists of 512
equally-sized sectors of 512 bytes each. The 16 KB
lockable Boot Block is intended for storage of the
system BIOS boot code. The boot code is the first
piece of code executed each time the system is
powered on or rebooted.
The V29C51400 is available in two versions: the
V29C51400T with the Boot Block address starting
from 7C000H to 7FFFFH, and the V29C51400B
with the Boot Block address starting from 00000H
to 3FFFH.
Read Cycle
A read cycle is performed by holding both CE
and OE signals LOW. Data Out becomes valid only
when these conditions are met. During a read cycle
WE must be HIGH prior to CE and OE going LOW.
WE must remain HIGH during the read operation
for the read to complete (see Table 1).
Output Disable
Returning OE or CE HIGH, whichever occurs first
will terminate the read operation and place the l/O
pins in the HIGH-Z state.
Standby
The device will enter standby mode when the CE
signal is HIGH. The l/O pins are placed in the
HIGH-Z, independent of the OE input state.
Command Sequence
The V29C51400T/V29C51400B does not
provide the “reset” feature to return the chip to its
normal state when an incomplete command
sequence or an interruption has happened. In this
case, normal operation (Read Mode) can be
restored by issuing a “non-existent” command
sequence, for example Address: 5555H, Data FFH.
Byte Write Cycle
The V29C51400T/V29C51400B is programmed
on a byte-by-byte basis. The byte write operation is
initiated by using a specific four-bus-cycle
sequence: two unlock program cycles, a program
setup command and program data program cycles
(see Table 2).
During the byte write cycle, addresses are
latched on the falling edge of either CE or WE,
whichever is last. Data is latched on the rising edge
of CE or WE, whichever is first. The byte write cycle
can be CE controlled or WE controlled.
V29C51400T/V29C51400B Rev. 1.5 October 2000
10
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