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USS-820FD

USB Device Controller

Agere -> LSI Corporation 

USS-820FD

USB Device Controller

Data Sheet, Rev. 1

August 2004

Pin Information (continued)

Table 3. Pin Descriptions

48-Ball

TFSBGAC

Symbol* Type

Name/Description

C2

VDDA

P 3.3 V Power Supply for Analog PLL.

B1

XTAL1

I Crystal/Clock Input. If the internal oscillator is used, this is the crystal input.

If an external oscillator is used, this is the clock input.

C1

XTAL2

O Crystal/Clock Output. If the internal oscillator is used, this is the crystal

output. If an external oscillator is used, this output should be left unconnected.

D2

VDDT

P 3.3 V Power Supply for USB Transceiver.

D1

D MINUS I/O USB Differential Data Bus Minus.

E2

D PLUS I/O USB Differential Data Bus Plus.

E1

VSST

P Device Ground for USB Transceiver.

G1, H1, G2,

F1, F2

A[4:0]

I Address Bus. This is the address bus for the controller to access the register

set.

G3, H6, B4

VSS0, VSS1,

VSS2

P Device Ground.

B8, C7, F7, G4,

G6, G7, G8,

H2, H5, H7, H8

VSSX

P Device Ground.

H3

G5

A2

H4,B2

A1

F8

E7

DSA

O Data Set Available. Indicates one or more receive data sets are valid, or one

or more transmit data sets are empty (available). For compatibility with USS-

820 revision B, this output is 3-stated if MCSR.BDFEAT = 0.

USBR

O USB Reset Detected. Indicates a USB reset event has been detected on

USB. This pin will remain asserted until the SSR.RESET register bit is cleared

by firmware. For compatibility with USS-820 revision B, this output is 3-stated

if MCSR.BDFEAT = 0.

NC†

— No Connect.

VDD0, VDD1 P 3.3 V Power Supply.

DPPU

O DPLS Pull-Up. Can be used to supply power to the DPLS 1.5 kΩ pull-up

resistor to allow firmware to simulate a device physical disconnect. This pin is

directly controlled by the DPEN register bit.

RWUPN

I Remote Wake-Up (Active-Low). Device is initiating a remote wake-up from a

suspend condition. This input is ignored if SCR register bit RWUPE = 0.

SUSPN

O Suspend (Active-Low). USB suspend has been detected; chip has entered

suspend (low power) mode. This pin is deasserted when a wake-up event is

detected.

E8

IRQN

O Interrupt (Programmable Active-Low or Active-High). An interrupt signal

is sent to the controller whenever an event such as TX/RX done, SUSPEND,

RESUME, USBRESET, or SOF occurs.

D7

SOFN

O Start of Frame (Active-Low). This signal is asserted low for eight tCLK

periods when an SOF token is received.

D8

RESET

I Reset. When this signal is held high, all state machines and registers are set

at the default state.

C8

IOCSN

I Chip Select (Active-Low).

B7

WRN

I Control Register Write (Active-Low).

A8

A7, B6, A6, B5,

A5, A4, B3, A3

RDN

D[7:0]

I Control Register Read (Active-Low).

I/O Data Bus.

* Active-low signals within this document are indicated by an N following the symbol names.

† Pins marked as NC must have no external connections, except where noted.

8

Agere Systems Inc.

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