UPD75048CW Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD75048CW Datasheet PDF : 68 Pages
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µPD75048
9. RESET FUNCTION
When the RESET signal is input, the µPD75048 is reset and each hardware is initialized as indicated
in Table 9-1. Fig. 9-1 shows the reset operation timing.
RESET input
Wait
(31.3ms/4.19MHz)
Operation mode
or standby mode
HALT mode
Operation mode
Internal reset operation
Fig. 9-1 Reset Operation by RESET Input
Table 9-1 Status of Each Hardware after Reset (1/2)
Hardware
Program Counter (PC)
PSW
Carry Flag (CY)
Skip Flag (SK0-2)
Interrupt Status Flag (IST0)
Bank Enable Flag (MBE)
Stack Pointer (SP)
Data Memory (RAM)
Data Memory EEPROM
(EEPROM)
EEPROM Write Control
Register
General-Purpose Register
(X, A, H, L, D, E, B, C)
Bank Selection Register (MBS)
Basic Interval Counter (BT)
Timer
Mode Register (BTM)
RESET Input in Standby Mode
The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
Retained
0
0
The contents of bit 7 of address
0000H of the program memory is
set to MBE.
Undefined
Retained *
Contents of address being
written is undefined.
0
Retained
0
Undefined
0
RESET Input During Operation
The contents of the lower 5 bits
of address 0000H of the program
memory are set to PC12-8, and
the contents of address 0001H
are set to PC7-0.
Undefined
0
0
The contents of bit 7 of address
0000H of the program memory is
set to MBE.
Undefined
Undefined
Contents of address being
written is undefined.
0
Undefined
0
Undefined
0
Timer/Event Counter (T0)
0
0
Counter
Modulo Register
FFH
FFH
(TMOD0)
Mode Register (TM0)
0
0
TOE0, TOUT F/F
0, 0
0, 0
Watch Timer Mode Register (WM)
0
0
*: The data at the addresses 0F8H-0FDH of data memory is undefined by RESET input.
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