UPD63335 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD63335

STEREO SOUND CODEC

NEC => Renesas Technology 

µ PD63335

1.3.1 Switching external master clock frequency

To switch the external master clock frequency during ADC and DAC operation, use the following procedure.

(1) When using the Master mode (LRCLK, BIT_CLK generated internally)

<1> Set the DAC volume register (10h, 11h) and the DAC master volume register (14h, 15h) to MUTENote 1.

<2> Switch the external master clock frequency.

<3> Set the LRCLK/BIT_CLK operation mode (if there is a change) (use the reset/clock status register (00h)).

<4> Set the audio format (if there is a change) (use the interface/timing register (01h)).

<5> Set the DAC volume register (10h, 11h) and DAC master volume register (14h, 15h)Note 2

Notes 1. The instant that the external master clock frequency is switched, noise may occur. For this reason,

before switching the external master clock, set the volume for the DAC output to MUTE.

2. To prevent popping noises, after switching the external master clock frequency and following the

lapse of an interval of time sufficient for three or more LRCLK cycles to be supplied, cancel the

MUTE setting of the volume for the DAC output.

Also handle the ADC output data (SO) as valid data once the same interval of time has elapsed.

(2) When using the slave mode (LRCLK, BIT_CLK supplied from external)

<1> Set the DAC volume register (10h, 11h) and the DAC master volume register (14h, 15h) to MUTENote 1.

<2> Power down the ADC and DAC (use the power down control register (18h)).

<3> Switch the external master clock, LRCLK, BIT_CLK frequency.

<4> Set the LRCLK/BIT_CLK operation mode (if there is a change) (use the reset/clock status register (00h)).

<5> Set the audio format (if there is a change) (use the interface/timing register (01h)).

<6> Cancel ADC, DAC power down (use the power down control register (18h)).

<7> Set the DAC volume register (10h, 11h) and DAC master volume register (14h, 15h)Note 2.

Notes 1. Immediately after the ADC and DAC are powered down, noise may occur in the ADC and DAC

outputs. For this reason, before powering down the ADC and DAC, set the volume for the DAC

output to MUTE.

2. To prevent popping noises, after canceling power down and following the lapse of an interval of time

sufficient for three or more LRCLK cycles to be supplied, cancel the MUTE setting of the volume for

the DAC output. Also handle the ADC output data (SO) as valid data once the same interval of time

has elapsed.

Data Sheet S15003EJ6V0DS

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