UPD63335 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD63335

STEREO SOUND CODEC

NEC => Renesas Technology 

µ PD63335

CONTENTS

1. DESCRIPTION OF FUNCTIONS ........................................................................................................................... 8

1.1 Analog Input Block ........................................................................................................................................ 8

1.2 Analog Output Block ..................................................................................................................................... 8

1.3 Clock ............................................................................................................................................................... 8

1.3.1 Switching external master clock frequency .................................................................................. 9

1.4 Reset ............................................................................................................................................................. 10

1.5 Pin to Connect Noise-Reducing Capacitor................................................................................................ 10

1.6 Digital Interfaces.......................................................................................................................................... 11

1.6.1 Serial command interface ............................................................................................................. 11

1.6.2 Serial data interface....................................................................................................................... 12

1.6.3 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:0:0:0 ............................................................ 16

1.6.4 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:0:0:1 ............................................................ 16

1.6.5 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:0:1:0 ............................................................ 17

1.6.6 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:0:1:1 ............................................................ 17

1.6.7 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:0:0 ............................................................ 18

1.6.8 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:0:1 ............................................................ 18

1.6.9 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:1:0 ............................................................ 19

1.6.10 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 0:1:1:1 ............................................................ 19

1.6.11 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:0:0:0 ............................................................ 20

1.6.12 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:0:0:1 ............................................................ 20

1.6.13 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:0:1:0 ............................................................ 21

1.6.14 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:0:1:1 ............................................................ 21

1.6.15 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:1:0:0 ............................................................ 22

1.6.16 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:1:0:1 ............................................................ 22

1.6.17 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:1:1:0 (initial value) ..................................... 23

1.6.18 Data format of FSDF2:FSDF1:FSDF0:LRCLKS = 1:1:1:1 ............................................................ 23

1.7 Usage Precautions ...................................................................................................................................... 23

2. REGISTERS........................................................................................................................................................... 24

2.1 Individual Registers..................................................................................................................................... 25

2.1.1 Serial command interface check bit (SICK)................................................................................. 25

2.1.2 Reset/clock status register (00h).................................................................................................. 25

2.1.3 Interface/timing register (01h) ...................................................................................................... 26

2.1.4 Input select register (02h) ............................................................................................................. 27

2.1.5 ADC input gain registers (03h, 04h) ............................................................................................. 28

2.1.6 IN1 volume registers (05h, 06h).................................................................................................... 29

2.1.7 IN2 volume registers (07h, 08h).................................................................................................... 30

2.1.8 IN3 volume registers (09h, 0Ah) ................................................................................................... 31

2.1.9 IN4 volume registers (0Bh, 0Ch)................................................................................................... 32

2.1.10 IN5 volume register (0Dh) ............................................................................................................. 33

2.1.11 MIC volume register (0Eh)............................................................................................................. 34

2.1.12 IN6 volume register (0Fh).............................................................................................................. 35

2.1.13 DAC volume registers (10h, 11h).................................................................................................. 36

2.1.14 OUT master volume registers (12h, 13h) ..................................................................................... 37

6

Data Sheet S15003EJ6V0DS

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