UPD63210GT Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD63210GT Datasheet PDF : 18 Pages
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µPD63210, 63210L
3.2 Data Input Circuit
(1) Input data format
Data on MSB first, 2’s compliment, and backward justification is input.
(2) Selection of input data bit length
An input data bit length is selected by the BSEL (No.14) pin.
Table 3-2. Selection of Input Data Bit Length
Input Data Bit Length
16 bits
18 bits
BSEL
L
H
(3) Data input timing chart
SDI and LRCKI is incorporated in the internal shift register at the rising edge of BCKI. The SDI, LRCKI, and
BCKI waveforms must satisfy the conditions in the electrical specifications (such as VIH, VIL under DC
characteristics; and tBWH, tBWL, tBW, tDS, tDH, tLRS, and tLRH under AC characteristics).
SDI considers the 16 bits (when BSEL = L; 18 bits when BSEL = H) preceding the change point of LRCKI to be
valid data.
Regarding the combination of system clock selection and input data length selection, the conditions for
inputtable BCKI are shown in Table 3-3.
BCKI
32fs
48fs
64fs
Table 3-3. Limitations on BCKI
384fs
512fs
(CKSEL = L)
(CKSEL = H)
16 bits
18 bits
16 bits
18 bits
(BSEL = L) (BSEL = H) (BSEL = L) (BSEL = H)
-
-
-
-
The data input timing charts are shown in Figure 3-3 and Figure 3-4.
Figure 3-3. Data Input Timing Chart (when BSEL = L)
BCKI
SDI
LRCKI
Continuous
Continuous
Invalid
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Invalid
Lch data
MSB
LSB
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Rch data
1/fs
Figure 3-4. Data Input Timing Chart (when BSEL = H)
BCKI
SDI
LRCKI
Continuous
Continuous
MSB
LSB
MSB
LSB
Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 Invalid 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
Lch data
Rch data
1/fs
9
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