UPD6379A Ver la hoja de datos (PDF) - NEC => Renesas Technology
Número de pieza
componentes Descripción
Fabricante
UPD6379A Datasheet PDF : 16 Pages
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µPD6379, 6379A, 6379L, 6379AL
(2) Output signal updating timing
The L.OUT and R.OUT signals are updated after the input of 3.5 clocks following the change point indicating
the end of the LRCK pin R-ch data input period. Therefore, when the clock is supplied to CLK only during
D/A conversion, the clock must be stopped after the L.OUT and R.OUT signals corresponding to the last input
data are output. Be aware that the L.OUT and R.OUT signals corresponding to the last sample data are not output,
especially when the clock is supplied to CLK only during a sample data period.
Fig. 4-3 Output Timing Chart (1) (for continuous clocks)
3.5 CLK
CLK
MSB
LSB
MSB
LSB
SI 1 2 3 4 13 14 15 16 Invalid 1 2 3 4
13 14 15 16
Invalid
L-ch data (N)
R-ch data (N)
123
LRCK
(µPD6379, 6379L)
LRCK
(µPD6379A, 6379AL)
Delay
L.OUT
L-ch output (N–1)
L-ch output (N)
R.OUT
R-ch output (N–1)
R-ch output (N)
Fig. 4-4 Output Timing Chart (2) (when there is an interval which the clock is stopped)
CLK stop
CLK
3.5 CLK
CLK stop
MSB
SI 1 2 3 4
LSB
MSB
13 14 15 16 Invalid 1 2 3 4
LSB
13 14 15 16 Invalid
1234 5
LRCK
(µPD6379, 6379L)
LRCK
(µPD6379A, 6379AL)
L-ch data (N)
R-ch data (N)
Delay
L.OUT
L-ch output (N–1)
L-ch output
(N)
R.OUT
R-ch output (N–1)
R-ch output
(N)
(3) Countermeasures against shock noise
It is recommended that a mute circuit be connected to the next stage of the D/A converter. If a mute circuit is
not provided, shock noise may occur when power is applied.
12
Data Sheet S11588EJ4V0DS00
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