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UPD16782P Ver la hoja de datos (PDF) - NEC => Renesas Technology

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UPD16782P Datasheet PDF : 26 Pages
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µPD16782
5. FUNCTIONAL DESCRIPTION
5.1 Multiplexer Circuit
This circuit selects RGB video signals input to the C1 to C3 pins according to the pixel array of the liquid crystal panel,
and outputs the signals to the S1 through S300 pins.
Vertical stripe array, single-/double-side delta array, or mosaic array can be selected by using the MP/TH and MP/1.5
pins.
5.1.1 Vertical stripe array mode (MP/TH = L, MP/1.5 = L)
In this mode, the relation between video signals C1 to C3, and output pins is as shown below. This mode is used to drive
a panel of vertical stripe array. In this mode, the multiplexer circuit is in the through status.
Table 51. Relation between Video Signals C1 to C3, and Output Pins (during right shift)
Line No. (number
of INHs)
RESET
INH
S1 to S300
Sampling
0
H
L
C1 (C3)
Output
1
L
C1 (C3)
Output
2
L
C1 (C3)
Output
3
L
C1 (C3)
:
:
:
:
Remark ( ) indicates the case of left shift.
S2 to S299
Sampling
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
Output
C2 (C2)
:
S3 to S298
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
S4 to S297 ... S299 to S2 S300 to S1
Sampling
C1 (C3)
Output
C1 (C3)
Output
C1 (C3)
Output
C1 (C3)
:
... Sampling
C2 (C2)
... Output
C2 (C2)
... Output
C2 (C2)
... Output
C2 (C2)
...
:
Sampling
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
Output
C3 (C1)
:
Figure 51. Pixel Arrangement of Vertical Stripe Array and Multiplexer Operation
R C1
B C2 µPD16782
G C3
S1
S2
Right shift (R,/L = "H"), MP/TH = "L", MP/1.5 = "L"
S3
S4
S5
S6
S7
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
R
B
G
R
B
G
R
Data Sheet S15806EJ1V0DS
9

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