UPD16750N Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD16750N Datasheet PDF : 24 Pages
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µPD16750
4. PIN FUNCTIONS
Pin Symbol
Pin Name
Description
S1 to S384
Driver output
The D/A converted 256-gray-scale analog voltage is output.
D00 to D07
D10 to D17
D20 to D27
Display data input
The display data is input with a width of 48 bits, viz., the gray scale data (8 bits) by 6 dots (2
pixels).
DX0: LSB, DX7: MSB
D30 to D37
D40 to D47
D50 to D57
R,/L
STHR
STHL
CLK
STB
POL
POL21
POL22
LPC
V0 to V15
VDD1
VDD2
VSS1
Shift direction control These refer to the start pulse input/output pins when driver ICs are connected in cascade.
input
The shift directions of the shift registers are as follows.
R,/L = H : STHR input, S1 → S384, STHL output
R,/L = L : STHL input, S384 → S1, STHR output
Right shift start pulse R,/L = H : Becomes the start pulse input pin.
input/output
R,/L = L : Becomes the start pulse output pin.
Left shift start pulse R,/L = H : Becomes the start pulse output pin.
input/output
R,/L = L : Becomes the start pulse input pin.
Shift clock input
Refers to the shift register’s shift clock input. The display data is incorporated into the data
register at the rising edge of the 64th clock after the start pulse input, the start pulse output
reaches the high level, thus becoming the start pulse of the next-level driver.
Latch input
The contents of the data register are transferred to the latch circuit at the rising edge. And,
at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure
input of one pulse per horizontal period.
Polarity input
POL = L : The S2n–1 output uses V0 to V7 as the reference supply. The S2n output uses V8
to V15 as the reference supply.
POL = H : The S2n–1 output uses V8 to V15 as the reference supply. The S2n output uses V0
to V7 as the reference supply.
S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is
allowed the setup time(tPOL-STB) with respect to STB’s rising edge.
Data inversion
Data inversion can invert when display data is loaded.
POL21/22 = H : Data inversion loads display data after inverting it.
POL21/22 = L : Data inversion does not invert input data.
POL21: D00 to D07, D10 to D17, D20 to D27
POL22: D30 to D37, D40 to D47, D50 to D57
Low power control The output buffer constant current source is blocked, reducing current consumption. In lower
input
power mode (LPC = L: DC-level input possible), the ordinary static current consumption can
be reduced by approx. 33 %.
γ -corrected power Input the γ -corrected power supplies from outside by using operational amplifier. Make sure
supplies
to maintain the following relationships. During the gray scale voltage output, be sure to keep
the gray scale level power supply at a constant level.
VDD2 − 0.2 V > V0 > V1 > V2 > V3 > V4 > V5 > V6 > V7 > 0.5 VDD2
0.5 VDD2 − 0.3 V > V8 > V9 > V10 > V11 > V12 > V13 > V14 > V15 > VSS2 + 0.2 V
Logic power supply 3.3 V ± 0.3 V
Driver power supply 9.0 V ± 0.5 V
Logic ground
Grounding
VSS2
Driver ground
Grounding
4
Data Sheet S13719EJ4V0DS00
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