UPD16682A Ver la hoja de datos (PDF) - NEC => Renesas Technology
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UPD16682A Datasheet PDF : 55 Pages
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µPD16682A
3.2 Logic System Pins (1/3)
Pin Symbol
Pin Name
Pad No. I/O
Description
P,/S
/CS1,CS2
/RD(E)
/WR(R,/W)
C86
D0 to D5
D6 (SCL)
D7 (SI)
A0
TESTOUT
/RESET
Select data input
Chip select
Read (enable)
Write (read/write)
Interface select
Data bus
Data bus/serial clock
Data bus/serial data input
Data command
Test output
Reset
83
Input This pin is used to select between parallel data input and serial
data input.
P,/S = H : Parallel data input
P,/S = L : Serial data input
This setting cannot be switched after power-on. For details, see
5. DESCRIPTION OF FUNCTIONS.
8,9
Input These pins are used for the chip select signal. When /CS1 = L
and CS2 = H, this signal is active and can be used for I/O of data
and commands.
15
Input • When connected to 80 series CPU : active low
This pin connects the 80 series CPU’s RD signal. Data bus
output status is set when this signal is low.
• When connected to 68 series CPU : active high
It is used as the enable clock input pin for the 68 series CPU.
14
Input • When connected to 80 series CPU: active low
This pin connects the 80 series CPU's /WR signal. Signals on
the data bus are latched at the rising edge of the /WR signal.
• When connected to 68 series CPU
This pin is an input pin for read/write control signals.
R,/W = H : Read
R,/W = L : Write
82
Input This pin is used to select the CPU interface.
C86 = H : 68 series CPU interface
C86 = L : 80 series CPU interface
17 to 22
Input When used with a parallel interface, these pins correspond to
/Output data bus bits D0 to D5.
When used with a serial interface, they are pulled down
internally.
23
Input When used with a parallel interface, this pin corresponds to data
/Output bus bit D6.
When used with a serial interface, it is a serial clock input pin.
24
Input When used with a parallel interface, this pin corresponds to data
/Output bus bit D7.
When used with a serial interface, it is a serial data input pin.
12
Input This pin is connected to the LSB in the ordinary CPU address
bus to distinguish between data and commands.
A0 = H : Indicates that display data exists in bits D0 to D7.
A0 = L : Indicates that display control commands exist in bits D0
to D7.
6
Output This pin is used as a test output. Leave this pin open when used
for this purpose.
11
Input This pin is used to perform an internal reset when at low level.
CLS
Clock select
80
Input This pin is used to select the valid/invalid setting for the display
clock’s on-chip oscillation circuit.
CLS = H : On-chip oscillation circuit is valid
CLS = L : On-chip oscillation circuit is invalid (external input)
When CLS = L, a display clock is input via the CL pin.
8
Data Sheet S14402EJ1V0DS
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