UPD16654 Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD16654

150/154 OUTPUT TFT-LCD GATE DRIVE

NEC => Renesas Technology 

µPD16654

3. PIN FUNCTIONS

Pin Symbol

O1 to O154

STVR

STVL

CLK

R/L

OE1

OE2

OE3

Osel

VDD2

VCC

VSS

VEE1

VEE2

Pin Name

Driver output pins

Start pulse input/output pin

Shift clock input

Shift direction switching

input

Enable input

Number of output select

input

Positive power supply for

driver

Reference power supply

Ground (GND)

Negative power supply for

internal logic

Negative power supply for

driver

Description

Scan signal output pins that drive the gate electrode of a TFT-LCD.

The status of each output pin changes in synchronization with the rising edge

of shift clock CLK. The output voltage of the driver is VDD2 to VEE2.

Input/output pin of the internal shift register.

Start pulse signal is read at the rising edge of shift clock CLK and a scan

signal is output from the driver output pin. The interface of this terminal is

CMOS of 3.3 V.

When Osel signal is Low level, start pulse goes up to high level at the 154th

falling edge of shift clock CLK and goes down to low level at the 155th falling

edge.

And when Osel signal is High level, start pulse goes up to high level at the

150th falling edge of shift clock CLK and goes down to low level at the 151st

falling edge. The output level is VCC-VSS (logic level).

Shift clock input for the internal shift register. The contents of internal shift

register is shifted at the rising edge of CLK.

Shift direction switching input pin of the internal shift register.

R/L = H (right shift) : STVR → O1 → O2 ··· O153 → O154 → STVL

R/L = L (left shift) STVL → O154 → O153 ··· O2 → O1 → STVR

This pin fixes the driver output to the L level when it is high. However, the

shift register is not cleared. And, output enable actuation is asynchronous in

the clock. And, refer to “RELATIONS OF ENABLE INPUT AND OUTPUT

TERMINAL“.

Selects the number of outputs.

Osel = L : 154 outputs (SVGA)

Osel = H: 150 outputs (VGA, XGA, SXGA)

When Osel = H (150 outputs), O76 through O79 outputs of the shift register are

fixed to the VEE2 level. Fix this pin to VCC (VDD2) or VSS (VEE1) on TCP.

Shared with internal logic and driver

3.3 V ± 0.3 V. Reference power supply for level shifter: LS

Connect this pin to the system ground.

Negative power supply for internal logic

Negative power supply for driver

Caution 1. Power ON/OFF sequence

To prevent the µPD16654 from damage due to latch up, turn on power in the order VCC → VEE1,

VEE2 and VDD2 → logic input. Turn off power in the reverse order. Observe these power

sequences even during transition period.

4

Share Link: