UPD160083 Ver la hoja de datos (PDF) - NEC => Renesas Technology

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componentes Descripción

Fabricante

UPD160083

480-OUTPUT TFT-LCD SOURCE DRIVER (COMPATIBLE WITH 256-GRAY SCALES)

NEC => Renesas Technology 

µ PD160083

3. PIN FUNCTIONS

Pin Symbol

S1 to S480

D00P to D03P,

D00N to D03N

D10P to D13P,

D10N to D13N

D20P to D23P,

D20N to D23N

R,/L

(CMOS)

STHR

(CMOS)

STHL

(CMOS)

CLKP,

CLKN

(RSDS)

STB

(CMOS)

POL

(CMOS)

INV

(CMOS)

LPC

MODE1 to

MODE3

Pin Name

Driver

Display

data

(RSDS)

(1/2)

I/O

Description

Output The D/A converted 256-gray-scale analog voltage is output.

Input The display data is input with a width of 12 bits by double edge, viz., the gray scale

data (8 bits) by 3 dots (1 pixel).

Shift direction

control

Right shift start

pulse

Left shift start

Shift clock

Latch

Polarity

Data inversion

Low power control

Output short contro

Input

I/O

I/O

Input

Input

Input

Input

Input

Input

These refer to the start pulse input/output pins when driver ICs are connected in

cascade. The shift directions of the shift registers are as follows.

R,/L = H (VDD1 level): STHR input, S1 → S480, STHL output

R,/L = L (VSS1 level): STHL input, S480→ S1, STHR output

R,/L = H (VDD1 level): Becomes the start pulse input pin.

R,/L = L (VSS1 level): Becomes the start pulse output pin.

R,/L = H (VDD1 level): Becomes the start pulse output pin.

R,/L = L (VSS1 level): Becomes the start pulse input pin.

Refers to the shift register’s shift clock input. The display data is incorporated into

the data register at both of rising and falling edge.

At the falling edge of the 160th clock after the start pulse input, the start pulse

output reaches the high level, thus becoming the start pulse of the next-level driver.

The contents of the data register are transferred to the latch circuit at the rising

edge. And the output timing and output short function are controlled by MODE1 to

MODE3. Please refer to 8. RELATIONSHIP BETWEEN STB, POL, MODE1 to

MODE3 AND OUTPUT WAVEFORM for more detail. It is necessary to ensure

input of one pulse per horizontal period.

POL = H (VDD1 level): The S2n–1 output uses V0-V8 as the reference supply.

The S2n output uses V9-V17 as the reference supply.

POL = L (VSS1 level): The S2n–1 output uses V9-V17 as the reference supply.

The S2n output uses V0-V8 as the reference supply.

S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL

signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.

Data inversion can invert when display data is loaded.

INV = H (VDD1 level): Data inversion loads display data after inverting it.

INV = L (VSS1 level): Data inversion does not invert input data.

Please input DC signal. For details, refer to 6. DATA INVERSION.

LPC = L or open: Normal mode (default)

LPC = H: Low power mode (35% lower than noamal mode)

This pin is pulled down to the VSS1D inside the IC.

This pin controls the output short function.

MODE1

MODE2

MODE3 Output Short

Remark

H or open

X

X

Non-active Output short circuit OFF

L

H or open

X

Active

During STB = H

L

H or open H or open

During 34 CLK after STB falling

L

L

During 68 CLK after STB falling

Remark X: H or L

Output short function works only when POL signal is changed from previous line.

This pin is pulled up to VDD1D inside the IC.

4

Preliminary Product Information S16450EJ1V0PM00

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