UPD160062 Ver la hoja de datos (PDF) - NEC => Renesas Technology

Número de pieza

componentes Descripción

Fabricante

UPD160062

384-/360-OUTPUT TFT-LCD SOURCE DRIVER

NEC => Renesas Technology 

µ PD160062

4. PIN FUNCTIONS

Pin Symbol

S1 to S420

D00 to D05

D10 to D15

D20 to D25

D30 to D35

D40 to D45

D50 to D55

R,/L

Pin Name

Driver

Display data

Shift direction

control

STHR

STHL

CLK

Right shift start

pulse

Left shift start

pulse

Shift clock

STB

POL

Latch

Polarity input

POL21,

POL22

Data inversion

LPC

HPC

Bcont

Low power control

High power control

Bias control

I/O

Output

Input

(1/2)

Description

The D/A converted 64-gray-scale analog voltage is output.

The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by

6 dots (2 pixels).

DX0: LSB, DX5: MSB

Input

I/O

I/O

Input

Input

Input

Input

Input

Input

Input

The shift direction control pin of shift register. The shift directions of the shift

registers are as follows.

R,/L = H (right shift) : STHR input, S1 → S420, STHL output

R,/L = L (left shift) : STHL input, S420 → S1, STHR output

These refer to the start pulse I/O pins when driver ICs are connected in cascade.

Fetching of display data starts when H is read at the rising edge of CLK.

R,/L = H (right shift) : STHR input, STHL output

R,/L = L (left shift) : STHL input, STHR output

A H level should be input as the pulse of one cycle of the clock signal.

If the start pulse input is more than 2 CLK, the first 1 CLK of the H level input is

valid.

Refers to the shift register’s shift clock input. The display data is incorporated into

the data register at the rising edge. At the rising edge of the 70th clock after the

start pulse input, the start pulse output reaches the high level, thus becoming the

start pulse of the next-level driver. If 72 clock pulses are input after input of the

start pulse, input of display data is halted automatically. The contents of the shift

register are cleared at the STB’s rising edge.

The contents of the data register are transferred to the latch circuit at the rising

edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is

necessary to ensure input of one pulse per horizontal period.

POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output

uses V5 to V9 as the reference supply.

POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output

uses V0 to V4 as the reference supply.

S2n−1 indicates the odd output and S2n indicates the even output. Input of the POL

signal is allowed the setup time (tPOL-STB) with respect to STB’s rising edge.

Data inversion can invert when display data is loaded.

POL21: Invert/not invert of display data D00 to D05, D10 to D15, D20 to D25

POL22: Invert/not invert of display data D30 to D35, D40 to D45, D50 to D55

POL21, POL22 = H: Data inversion loads display data after inverting it.

POL21, POL22 = L: Data inversion does not invert input data.

Controls the write function of the driver section by digitally controlling the bypass

current of the output amplifier. Refer to 9. CURRENT CONSUMPTION

CONTROL FUNCTION for details.

This pin is pulled up to the VDD1 power supply inside the IC.

This pin can be used to finely control the bias current inside the output amplifier.

Refer to 9. CURRENT CONSUMPTION CONTROL FUNCTION for details.

When this fine-control function is not required, leave this pin open.

4

Data Sheet S16449EJ1V0DS

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