UJA1076TW/3V3 Ver la hoja de datos (PDF) - NXP Semiconductors.
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UJA1076TW/3V3 Datasheet PDF : 47 Pages
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NXP Semiconductors
5. Pinning information
5.1 Pinning
UJA1076
High-speed CAN core system basis chip
i.c. 1
i.c. 2
i.c. 3
V1 4
i.c. 5
RSTN 6
INTN 7
EN 8
SDI 9
SDO 10
SCK 11
SCSN 12
TXDC 13
RXDC 14
TEST1 15
WDOFF 16
Fig 2. Pin configuration
UJA1076
32 BAT
31 VEXCTRL
30 TEST2
29 VEXCC
28 WBIAS
27 i.c.
26 i.c.
25 i.c.
24 SPLIT
23 GND
22 CANL
21 CANH
20 V2
19 WAKE2
18 WAKE1
17 LIMP
015aaa109
5.2 Pin description
Table 2.
Symbol
i.c.
i.c.
i.c.
V1
i.c.
RSTN
INTN
EN
SDI
SDO
SCK
SCSN
TXDC
RXDC
TEST1
WDOFF
LIMP
Pin description
Pin
Description
1
internally connected; should be left floating
2
internally connected; should be left floating
3
internally connected; should be left floating
4
voltage regulator output for the microcontroller (5 V or 3.3 V depending on
SBC version)
5
internally connected; should be left floating
6
reset input/output to and from the microcontroller
7
interrupt output to the microcontroller
8
enable output
9
SPI data input
10
SPI data output
11
SPI clock input
12
SPI chip select input
13
CAN transmit data input
14
CAN receive data output
15
test pin; pin should be connected to ground
16
WDOFF pin for deactivating the watchdog
17
limp home output
UJA1076_2
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 02 — 27 May 2010
© NXP B.V. 2010. All rights reserved.
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