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UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

NXP Semiconductors. 

NXP Semiconductors

UJA1061

Fault-tolerant CAN/LIN fail-safe system basis chip

Table 2. Pin description …continued

Symbol

Pin Description

INH/LIMP 17 inhibit/limp-home output (BAT14 related, push-pull, default floating)

WAKE

18 local wake-up input (BAT42 related, continuous or cyclic sampling)

RTL

19 CAN termination resistor connection; in case of a CANL bus wire error this

line is terminated with a selectable impedance

V2

20 5 V voltage regulator output for CAN; connect a buffer capacitor to this pin

CANH

21 CANH bus line (HIGH in dominant state)

CANL

22 CANL bus line (LOW in dominant state)

GND

23 ground

RTH

24 CAN termination resistor connection; in case of a CANH bus wire error this

line is terminated with a selectable impedance

LIN

25 LIN bus line (LOW in dominant state)

RTLIN

26 LIN-bus termination resistor connection

BAT14

27 14 V battery supply input

n.c.

28 not connected

SYSINH

29 system inhibit output (BAT42 related; e.g. for controlling external DC-to-DC

converter)

V3

30 unregulated 42 V output (BAT42 related; continuous output, or Cyclic mode

synchronized with local wake-up input)

reserved

31 must be connected to ground (GND)

BAT42

32 42 V battery supply input (connect this pin to BAT14 in 14 V applications)

The exposed die pad at the bottom of the package allows better dissipation of heat from

the SBC via the printed-circuit board. The exposed die pad is not connected to any active

part of the IC and can be left floating, or can be connected to GND for the best EMC

performance.

UJA1061_6

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 06 — 9 March 2010

© NXP B.V. 2010. All rights reserved.

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