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UBA2037TS/N1,118 Datasheet PDF : 14 Pages
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NXP Semiconductors
UBA2037
Full bridge control IC for HID general lighting
Table 3. Driver
Gate driver output voltages as function of the logical levels at the pins BD, SU, DD and CLK.
Device
state
BD SU DD CLK GHL
GHR
GLL
GLR
Start-up 1 -
-
-
state
0-
-
-
0 (= VSHL)
0 (= VSHL)
0 (= VSHR)
0 (= VSHR)
0 (= VPGND) 0 (= VPGND)
1 (= VVDD) 1 (= VVDD)
Oscillation 1 -
-
-
state
00
-
-
0 (= VSHL)
0 (= VSHL)
0 (= VSHR)
0 (= VSHR)
0 (= VPGND) 0 (= VPGND)
1 (= VVDD) 1 (= VVDD)
0
1
1
1
0 (= VSHL) 1 (= VFSR) 1 (= VVDD) 0 (= VPGND)
01
01
10
1 (= VFSL) 0 (= VSHR) 0 (= VPGND) 1 (= VVDD)
0[1] 1 → 0[2] GHL
GHR
GLL
GLR
[1] If pin DD = 0 the bridge enters the state (oscillation state and pin BD = 0 and pin SU = 1) in the predefined
position: VGHL = VFSL, VGLR = VVDD, VGLL = VPGND, and VGHR = VSHR.
[2] Only if the level of pin CLK changes from logical 1 to 0, the level of outputs GHL, GHR, GLL and GLR
changes.
If there is no external clock available, the internal oscillator can be used. The design
equation for the bridge oscillator frequency is shown in Equation 1.
f bridge = -K----o---s--c---×-----R----1o---s--c---×-----C-----o--s---c
(1)
Rosc and Cosc are external components connected to the RC pin (Rosc connected to pin
VDD and Cosc connected to pin SGND). In this situation the pins VDD(CLK), CLK and
VSS(CLK) can be connected to SGND.
The clock signal, coming from either pin RC or pin CLK, can be divided by two in order to
obtain a 50 % duty-cycle gate drive signal. This can be achieved by applying a voltage to
the DD input lower than VIL(DD) (e.g. connect pin DD to pin SGND).
7.4 Non-overlap time
In the full bridge configuration the non-overlap time is defined as the time between turning
off the two conducting MOSFETs and turning on the two other MOSFETs. The
non-overlap time is realized by means of an adaptive non overlap circuit. With an adaptive
non-overlap, the application determines the duration of the non overlap and makes the
non-overlap time optimal for each frequency. The non-overlap time is determined by the
duration of the falling slope of the relevant half bridge voltage. The occurrence of a slope
is sensed internally. The minimum non-overlap time is internally fixed.
7.5 Start-up delay
A simple RC filter (R between pin VDD and pin SU; C between pin SU and pin SGND) or
a control signal from a processor can be used to make a start-up delay. This can be
beneficial for those applications in which building up the high voltage takes a larger
amount of time: A start-up delay will ensure that the HID system will not start up before
this high voltage has been reached.
UBA2037_1
Product data sheet
Rev. 01 — 30 October 2008
© NXP B.V. 2008. All rights reserved.
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