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TZA3044U(1998) Ver la hoja de datos (PDF) - Philips Electronics

Número de pieza
componentes Descripción
Fabricante
TZA3044U
(Rev.:1998)
Philips
Philips Electronics Philips
TZA3044U Datasheet PDF : 18 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
Philips Semiconductors
1.25 Gbits/s Gigabit Ethernet postamplifiers
Objective specification
TZA3044T; TZA3044U
Bonding pad locations
handbook, full pagewidth
AGND
n.c.
AGND
1.58(1) DIN
mm DINQ
AGND
TEST
VCCA
3 2 1 32 31 30 29 28
4
27
5
26
6
25
7
x
24
8
0
0
23
9
y
22
10
TZA3044U
21
11
20
12 13 14 15 16 17 18 19
VCCD
TEST
DGND
DOUT
DOUTQ
DGND
TEST
DGND
(1) Typical value.
Pad size: 90 × 90 µm.
1.58 mm(1)
MGR242
Fig.3 Bonding pad locations: TZA3044U.
FUNCTIONAL DESCRIPTION
The TZA3044 accepts up to 1.25 Gbits/s Gigabit Ethernet
data streams, with amplitudes from 2 mV (p-p) up to
1 V (p-p) single-ended. The input signal will be amplified
and limited to differential PECL output levels (see Fig.1).
The input buffer A1 presents an impedance of
approximately 4.5 kto the data stream on the inputs DIN
and DINQ. The input can be used both single-ended and
differential, but differential operation is preferred for better
performance.
Because of the high gain of the postamplifier, a very small
offset voltage would shift the decision level in such a way
that the input sensitivity decreases drastically. Therefore a
DC offset compensation circuit is implemented in the
TZA3044, which keeps the input of buffer A3 at its toggle
point in the absence of any input signal.
An input signal level detection is implemented to check if
the input signal is above the user-programmed level.
The outcome of this test is available at the PECL
outputs ST and STQ. This flag can also be used to prevent
the PECL outputs DOUT and DOUTQ from reacting to
noise in the absence of a valid input signal, by connecting
the output STQ to the input JAM. This insures that data will
only be transmitted when the input signal-to-noise ratio is
sufficient for low bit error rate system operation.
PECL logic
The logic level symbol definitions for PECL are shown in
Fig.4.
Input biasing
The input pins DIN and DINQ are DC biased at
approximately 2.55 V by an internal reference generator
(see Fig.5). The TZA3044 can be DC coupled, but AC
coupling is preferred. In case of DC coupling, the driving
source must operate within the allowable input signal
range (2.0 V to VCCA + 0.5 V). Also a DC offset voltage of
1998 Jul 07
5

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