MX7837 Ver la hoja de datos (PDF) - Maxim Integrated

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MX7837

Complete, Dual, 12-Bit Multiplying DACs

Maxim Integrated 

Complete, Dual, 12-Bit

Multiplying DACs

LDAC

CS

WR

A0

A1

DAC A LATCH

DAC B LATCH

12

12

4

DAC A

MS

INPUT

LATCH

8

DAC A

LS

INPUT

LATCH

4

DAC B

MS

INPUT

LATCH

8

DAC B

LS

INPUT

LATCH

8

DB7 DB0

Figure 4. MX7837 Input Control Logic

CS, WR, A0, and A1 control data loading to the input

latches. The eight data inputs accept right-justified

data, which can be loaded to the input latches in any

sequence. If LDAC is held high, loading data to the

input latches will not change the analog output. A0

and A1 determine which input latch will receive the

data when CS and WR are low. Table 2 shows the

control logic truth table.

Table 2. MX7837 Truth Table

CS WR A1 A0 LDAC

Function

1XXX

X1XX

0000

0001

0010

0011

11XX

1 No Data Transfer

1 No Data Transfer

1 DAC A LS Input Latch Transparent

1 DAC A MS Input Latch Transparent

1 DAC B LS Input Latch Transparent

1 DAC B MS Input Latch Transparent

0

Updated Simultaneously from

the Respective Input Latches

X = Don't Care

The LDAC input controls 12-bit data transfer from the

input latches to the DAC latches. When LDAC is taken

low, both DAC latches (thus, both analog outputs) are

updated simultaneously. When LDAC is low, the DAC

latches are transparent; DAC data is latched on the ris-

ing edge of LDAC. The LDAC input is asynchronous

A0/A1

CS

WR

DATA

LDAC

ADDRESS VALID

t6

t7

t1

t3

t2

t4

t5

VALID DATA

t8

Figure 5. MX7837 Write-Cycle Timing Diagram

and independent of WR. This is useful in many appli-

cations, especially in updating multiple MX7837s simul-

taneously. However, be careful when exercising LDAC

during a write cycle; if an LDAC operation overlaps a

CS and WR operation, invalid data may be latched to

the output. To avoid this, LDAC must remain low after

CS or WR have returned high for a period equal to or

greater than t8, the minimum LDAC pulse width.

Unipolar Binary Operation

Figure 6 shows DAC A (MX7837/MX7847) connected

for unipolar binary operation. Similar connections

apply for DAC B. When VIN is an AC signal, the circuit

performs 2-quadrant multiplication. Table 3 shows the

code table for this circuit. On the MX7847, the RFB

feedback resistor is internally connected to VOUT.

Table 3. Unipolar Code Table

DAC Latch Contents

MSB

LSB

Analog Output, VOUT

1111 1111 1111

−VIN

×

 4095 

 4096 

1000 0000 0000

−VIN

×

 2048 

 4096 

=

−

1

2

VIN

0000 0000 0001

−VIN

×

 1

 4096 

0000 0000 0000

0V

Note :

1LSB

=

 VIN 

 4096 

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