TSC80251G2D(2006) Ver la hoja de datos (PDF) - Atmel Corporation

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TSC80251G2D
(Rev.:2006)

8/16-bit Microcontroller with Serial Communication Interfaces

Atmel Corporation 

Signals

4135F–8051–11/06

AT/TSC8x251G2D

Table 2. Product Name Signal Description

Signal

Name Type Description

18th Address Bit

A17

O

Output to memory as 18th external address bit (A17) in extended bus

applications, depending on the values of bits RD0 and RD1 in UCONFIG0

byte (see Table 13, Page 20).

17th Address Bit

A16

O

Output to memory as 17th external address bit (A16) in extended bus

applications, depending on the values of bits RD0 and RD1 in UCONFIG0

byte (see Table 13, Page 20).

Alternate

Function

P1.7

P3.7

A15:8(1)

O

Address Lines

Upper address lines for the external bus.

P2.7:0

AD7:0(1)

I/O

Address/Data Lines

Multiplexed lower address lines and data for the external memory.

P0.7:0

Address Latch Enable

ALE

O

ALE signals the start of an external bus cycle and indicates that valid

address information are available on lines A16/A17 and A7:0. An external

–

latch can use ALE to demultiplex the address from address/data bus.

Real-time Asynchronous Wait States Input

When this pin is active (low level), the memory cycle is stretched until it

becomes high. When using the Product Name as a pin-for-pin replacement

AWAIT#

I for a 8xC51 product, AWAIT# can be unconnected without loss of

–

compatibility or power consumption increase (on-chip pull-up).

Not available on DIP package.

CEX4:0

PCA Input/Output pins

I/O CEXx are input signals for the PCA capture mode and output signals for

the PCA compare and PWM modes.

P1.7:3

External Access Enable

EA# directs program memory accesses to on-chip or off-chip code memory.

For EA# = 0, all program memory accesses are off-chip.

EA#

I For EA# = 1, an access is on-chip ROM if the address is within the range of

–

the on-chip ROM; otherwise the access is off-chip. The value of EA# is

latched at reset.

For devices without ROM on-chip, EA# must be strapped to ground.

ECI

O

PCA External Clock input

ECI is the external clock input to the 16-bit PCA timer.

P1.2

MISO

SPI Master Input Slave Output line

I/O

When SPI is in master mode, MISO receives data from the slave

peripheral. When SPI is in slave mode, MISO outputs data to the master

controller.

P1.5

MOSI

SPI Master Output Slave Input line

I/O When SPI is in master mode, MOSI outputs data to the slave peripheral.

When SPI is in slave mode, MOSI receives data from the master controller.

P1.7

INT1:0#

External Interrupts 0 and 1

I

INT1#/INT0# inputs set IE1:0 in the TCON register. If bits IT1:0 in the

TCON register are set, bits IE1:0 are set by a falling edge on INT1#/INT0#.

If bits IT1:0 are cleared, bits IE1:0 are set by a low level on INT1#/INT0#.

P3.3:2

7

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