5962-0054001VXC Ver la hoja de datos (PDF) - Atmel Corporation
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5962-0054001VXC Datasheet PDF : 42 Pages
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Instruction Set
TSC695F instructions fall into six functional categories: load/store, arithmetic/logi-
cal/shift, control transfer, read/write control register, floating-point, and miscellaneous.
Please refer to SPARC V7 Instruction-set Manual.
Note: The execution of IFLUSH will cause an illegal instruction trap.
On-chip Peripherals
Memory Interface
The TSC695F is designed to allow easy interfacing to internal/external memory
resources.
Table 2. Memory Mapping
Memory Contents
Start Address Size (bytes)
Data Size and Parity Options
Boot PROM
0x 00000000
128K → 16M 8-bit mode No parity/-No EDAC/-Only byte write
40-bit mode Parity + EDAC mandatory/-Only word write
Extended PROM
0x 01000000
Max: 15M
8-bit mode No parity/-No EDAC/-Only byte write
40-bit mode Parity + EDAC mandatory/-Only word write
Exchange Memory 0x01F00000 4k → 512k
Parity + EDAC option/-Only word write
System Registers 0x01F80000 512K (124 used) Parity/-Only word read/write access
RAM (8 blocks)
0x 0200 0000
8*32K → 8*4M
Parity + EDAC option/-All data sizes allowed
Extended RAM
0x 0400 0000
Max: 192M
I/O Area 0
0x 1000 0000
0 → 16M
Parity option/-All data sizes allowed
I/O Area 1
0x 1100 0000
0 → 16M
I/O Area 2
0x 1200 0000
0 → 16M
I/O Area 3
0x 1300 0000
0 → 16M
Extended I/O Area 0x14000000 Max: 1728M
Extended General 0x80000000 Max: 2G
No parity/-All data sizes allowed
System Registers
The system registers are only writable by IU in the supervisor mode or by DMA during
halt mode.
Table 3. System Registers Address Map
System Register Name
System Control Register
Software Reset
Power Down
System Fault Status Register
Failing Address Register
Error & Reset Status Register
Test Control Register
SYSCTR
SWRST
PDOWN
SYSFSR
FAILAR
ERRRSR
TESCTR
Address
0x 01F8 0000
0x 01F8 0004
0x 01F8 0008
0x 01F8 00A0
0x 01F8 00A4
0x 01F8 00B0
0x 01F8 00D0
6 TSC695F
4118J–AERO–08/04
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