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5962-0054001VXC

Rad-Hard 32-bit SPARC Embedded Processor

Atmel Corporation 

TSC695F

Product Description

Integer Unit

Floating-point Unit

The Integer Unit (IU) is designed for highly dependable space and military applications,

and includes support for error detection. The RISC architecture makes the creation of a

processor that can execute instructions at a rate approaching one instruction per pro-

cessor clock possible.

To achieve that rate of execution, the IU employs a four-stage instruction pipeline that

permits parallel execution of multiple instructions.

• Fetch - The processor outputs the instruction address to fetch the instruction.

• Decode - The instruction is placed in the instruction register and is decoded. The

processor reads the operands from the register file and computes the next

instruction address.

• Execute - The processor executes the instruction and saves the results in temporary

registers. Pending traps are prioritized and internal traps are taken during this stage.

• Write - If no trap is taken, the processor writes the result to the destination register.

All four stages operate in parallel, working on up to four different instructions at a time. A

basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles.

By the time it reaches the write stage, three more instructions have entered and are

moving through the pipeline behind it. So, after the first four cycles, a single-cycle

instruction exits the pipeline and a single-cycle instruction enters the pipeline on every

cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but

they are called single cycle because with this type of instruction the processor can com-

plete one instruction per cycle after the initial four-cycle delay.

The FLoating Point Unit (FPU) is designed to provide execution of single and double-

precision floating-point instructions concurrently with execution of integer instructions by

the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard.

The FPU is designed for highly dependable space and military applications, and

includes support for concurrent error detection and testability.

The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and

write stages (F, D, E and W). The fetch unit captures instructions and their addresses

from the data and address buses. The decode unit contains logic to decode the floating-

point instruction opcodes. The execution unit handles all instruction execution. The exe-

cution unit includes a floating-point queue (FP queue), which contains stored floating-

point operate (FPop) instructions under execution and their addresses. The execution

unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon

the IU to access all addresses and control signals for memory access. Floating-point

loads and stores are executed in conjunction with the IU, which provides addresses and

control signals while the FPU supplies or stores the data. Instruction fetch for integer

and floating-point instructions is provided by the IU.

The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR

is a 32-bit status and control register. It keeps track of rounding modes, floating-point

trap types, queue status, condition codes, and various IEEE exception information. The

floating-point queue contains the floating-point instruction currently under execution,

along with its corresponding address.

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4118J–AERO–08/04

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