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5962-0054001VXC

Rad-Hard 32-bit SPARC Embedded Processor

Atmel Corporation 

Table 4. Synchronous Traps (Continued)

Trap

Priority

Data access exception

(Error on data load)

10

Tag overflow

11

Trap instructions

12

Trap Type (tt) Comments

Idem “instruction access”

09h

System register access violation

0Ah

TADDccTV and TSUBccTV instructions

80h to FFh Trap on integer condition codes (Ticc)

Table 5. Interrupts or Asynchronous Traps

Trap

Priority

Watchdog time-out

13

External INT 4

14

Real time clock timer

15

General purpose timer

16

External INT 3

17

External INT 2

18

DMA time-out

19

DMA access error

20

UART Error

21

Correctable error in memory

22

Data ready

UART B Transmitter ready

23

Data ready

UART A Transmitter ready

24

External INT 1

25

External INT 0

26

Masked hardware errors

27

Trap Type (tt) Comments

1Fh

Internal or external (EWDINT pin)

1Eh

EXTINTAK on only one of EXTINT[4:0]

1Dh

–

1Ch

–

1Bh

EXTINTAK on only one of EXTINT[4:0]

1Ah

EXTINTAK on only one of EXTINT[4:0]

19h

–

18h

–

17h

–

16h

Data read OK but source not updated

–

15h

–

14h

13h

EXTINTAK on only one of EXTINT[4:0]

12h

EXTINTAK on only one of EXTINT[4:0]

Logical OR of:

IU hardware error masked

IU error mode masked

11h

System hardware error masked

It is possible to mask each individual interrupt (except Watchdog time-out). The interrupts in the Interrupt Pending Register

are cleared automatically when the interrupt is acknowledged.

By programming the Interrupt Shape Register, it is possible to define the external interrupts to either be active low or active

high and to define the external interrupts to either be edge or level sensitive.

10 TSC695F

4118J–AERO–08/04

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