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TS68C429A

CMOS ARINC 429 Multichannel Receiver/ Transmitter (MRT)

Atmel Corporation 

TS68C429A

To detect the end of the message, the Gap-Controller waits for a Gap after the last

received bit. To do so, at each CLK ARINC cycle, a counter is incremented and com-

pared to the content of the Gap-Register which has the user programmed value. If both

values are equal, the counter is stopped and an internal end of message signal is gener-

ated. This counter is reseted on the falling edge of the rebuilt clock. Figure 9 shows the

gap detection principle.

When the end of message is detected, the TS68C429A verifies the following points:

• the number of received bits must be 32,

• if requested the message parity (see “Register Description” on page 17) is

compared to the parity bit of the message,

• the message label must be equal to one of the label stored in the Label Control

Matrix,

• the Buffer is empty (that is: the last message has been read). The corresponding bit

in the Status-register (see logical interface unit), has been cleared,

• when all four conditions are met, the message is transferred from the Shift-register

to the Buffer and the corresponding bit is set in the Status-register. If the interrupt

mode is enabled (see “General Circuit Control” on page 24) the IRQRX line is

activated.

If not, reception of a new message is enabled, see Note.

If only the message parity is incorrect, an interrupt can be generated (see “Register

Description” on page 17).

The Buffer is seen as two 16-bit word registers, the Most Significant Word of the mes-

sage (MSW) is contained in the lower address, the Less Significant Word of the

message (LSW) is contained in the upper address. The MSW should be read first

because reading the LSW will release the buffer and allow transfer of a new message

from the Shift-register.

15

2120A–HIREL–08/02

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