TS68C429A Ver la hoja de datos (PDF) - Atmel Corporation

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TS68C429A

CMOS ARINC 429 Multichannel Receiver/ Transmitter (MRT)

Atmel Corporation 

Table 8. Timing Characteristic (Continued)

Number

Symbol

Parameter

Min

18

tSHRWI

CS or LDS/UDS high to R/W invalid

0

19

tDKLDIH

DTACK low to data in hold time

0

20

tSHDOH

CS or LDS/UDS or IACKxx high data out hold

time

0

Note: 1. T/G = Tested/Guaranteed.

Max

-

-

-

T/G(1)

G

G

G

Unit

ns

ns

ns

Functional

Description

Receiver Channel Unit

(RCU)

Overview

Inputs

Figure 8.

The RCU is composed of 8 ARINC receiver channels and has per channel:

• a serial to parallel converter to translate the two serial signals in two 16-bit words.

• a memory to store the authorized labels,

• a control logic to check the validity of the received message.

• a buffer to keep the last valid received message.

Each receiver channel has two input lines, receiving line high (RxiH) and receiving line

low (RXiL) which are not directly compatible with the bipolar modulated ARINC line. This

ARINC three-level state signals (“HIGH”, “NULL”, “LOW”) should be demultiplexed to

generate the two RZ lines according to Figure 8.

Description

Each channel has a test mode in which the input signals (RXiH, RXiL), are internally

connected to the third Transmit Channel Lines. This selection is done by programming

the Test bit in the receiver control register (see “Register Description” on page 17)

except this difference, the TS68C429A behaves exactly the same manner in the two

modes. The receiver channel block diagram is given in Figure 9.

ARINC signals being asynchronous, the RCU first rebuilds the received clock in order to

transfer the data within the shift-register and when the Gap-controller has detected the

end of the message, tests the message validity according to the criteria listed hereafter.

14 TS68C429A

2120A–HIREL–08/02

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