AD1870JR Ver la hoja de datos (PDF) - Analog Devices
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AD1870JR Datasheet PDF : 20 Pages
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AD1870
Layout and Decoupling Considerations
Obtaining the best possible performance from the AD1870
requires close attention to board layout. Adhering to the follow-
ing principles will produce typical values of 92 dB dynamic range
and 90 dB S/(THD + N) in target systems. Schematics and lay-
out artwork of the AD1870 Evaluation Board, which implement
these recommendations, are available from Analog Devices.
The principles and their rationales are listed below. The first
two pertain to bypassing and are illustrated in Figure 3.
4.7F
4.7F
470pF
NPO
0.1F
0.1F
470pF
NPO
470pF
NPO
5V
DIGITAL
AGNDL VREFL VREFR AGNDR CAPR2 CAPR1
0.1F
470pF
NPO
CAPL2
CAPL1
AGND AVDD
AD1870
CLKIN
DVDD1 DGND1 DGND2 DVDD2
OSCILLATOR
0.1F
10nF
10nF
1F
1F
1F
5V
5V
ANALOG DIGITAL
5V
DIGITAL
Figure 3. Recommended Bypassing and Oscillator Circuits
There are two pairs of digital supply pins on opposite sides of
the part (Pins 4 and 5, and Pins 24 and 25). The user should
tie a bypass chip capacitor (10 nF ceramic) in parallel with a
decoupling capacitor (1 µF tantalum) on EACH pair of supply
pins as close to the pins as possible. The traces between these
package pins and the capacitors should be as short and as wide
as possible. This will prevent digital supply current transients
from being inductively transmitted to the inputs of the part.
Use a 0.1 µF chip analog capacitor in parallel with a 1.0 µF
tantalum capacitor from the analog supply (Pin 9) to the analog
ground plane. The trace between this package pin and the
capacitor should be as short and as wide as possible.
The AD1870 should be placed on a split ground plane. The
digital ground plane should be placed under the top end of the
package, and the analog ground plane should be placed under
the bottom end of the package as shown in Figure 4. The split
should be between Pins 8 and 9 and between Pins 20 and 21.
The ground planes should be tied together at one spot under-
neath the center of the package with an approximately 3 mm
trace. This ground plane technique also minimizes RF transmis-
sion and reception.
LRCK 1
WCLK 2
BCLK 3
DVDD1 4
DGND1 5
RDEDGE 6
S/M 7
384/256 8
AVDD 9
VINL 10
CAPL1 11
CAPL2 12
AGNDL 13
VREFL 14
DIGITAL GROUND PLANE
ANALOG GROUND PLANE
28 CLKIN
27 TAG
26 SOUT
25 DVDD2
24 DGND2
23 RESET
22 MSBDLY
21 RLJUST
20 AGND
19 VINR
18 CAPR1
17 CAPR2
16 AGNDR
15 VREFR
Figure 4. Recommended Ground Plane
Each reference pin (14 and 15) should be bypassed with a 0.1 µF
ceramic chip capacitor in parallel with a 4.7 µF tantalum capaci-
tor. The 0.1 µF chip cap should be placed as close to the pack-
age pin as possible, and the trace to it from the reference pin
should be as short and as wide as possible. Keep this trace away
from any analog traces (Pins 10, 11, 12, 17, 18, 19). Coupling
between input and reference traces will cause even order harmonic
distortion. If the reference is needed somewhere else on the
printed circuit board, it should be shielded from any signal
dependent traces to prevent distortion.
Wherever possible, minimize the capacitive load on the digital
outputs of the part. This will reduce the digital spike currents
drawn from the digital supply pins and help keep the IC sub-
strate quiet.
How to Extend SNR
A cost-effective method of improving the dynamic range and
SNR of an analog-to-digital conversion system is to use multiple
AD1870 channels in parallel with a common analog input. This
technique makes use of the fact that the noise in independent
modulator channels is uncorrelated. Thus every doubling of the
number of AD1870 channels used will improve system dynamic
range by 3 dB. The digital outputs from the corresponding deci-
mator channels have to be arithmetically averaged to obtain the
improved results in the correct data format. A microprocessor,
either general-purpose or DSP, can easily perform the averaging
operation.
–10–
REV. 0
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